Open Source Yacc Electronic Design Automation (EDA) Software

Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.

Xschem is a schematic capture program, it allows to create a hierarchical representation of circuits with a top down approach . By focusing on interconnections, hierarchy and properties a complex system (IC) can be described in terms of simpler building blocks. A VHDL, Verilog or Spice netlist can be generated from the drawn schematic, allowing the simulation of the circuit. Key feature of the program is its drawing engine written in C and using directly the Xlib drawing primitives; this gives top speed performance, even on very big circuits. I have succesfully managed to simulate complete VLSI projects with this tool, both digital (Verilog / VHDL) and analog (Spice). Schematics can be printed in SVG, PNG, PDF, formats. XSCHEM runs on Linux or other Unix-likes with Xorg server and on Windows with the Cygwin layer and required tools installed. Can be found also on github: https://github.com/StefanSchippers/xschem

An Electronic Definition Interchange Format (EDIF) parser which allows exports from one EDA schematic capture system (such as OrCad) for import into another (such as KiCad)

lilpM32 is a MIPS-like processor designed in Logisim, assembler program and documentation for them. Complete assembler and fully functional instruction set with I/O and subroutines features allow to write full-blown complicated programs.

Hierarchical VCD Viewer is new trace file viewer. It's based on Qt 3.3.4 (migrating to Qt 4.1) graphic library and its main feature is to provide a hierarchical view of VCD trace file.