Commits · v6.9.0 · Fábio Rafael Coutada da Cunha / Hog

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Apr 26, 2022
- FEATURE: LaunchSimulation uses HOG_SIMULATION_LIB_PATH by default · ff6d8178
  Davide Cieri authored Apr 26, 2022
  
  View commits for tag v6.9.0 v6.9.0
  
  ff6d8178
Apr 25, 2022
- removing extra space · 87e44477
  Davide Cieri authored Apr 25, 2022
  
  87e44477
- colon · a9805b92
  Davide Cieri authored Apr 25, 2022
  
  a9805b92
Apr 22, 2022
- missing semicolumn · 2477fa92
  Davide Cieri authored Apr 22, 2022
  
  2477fa92
- comma · be4bad6d
  Davide Cieri authored Apr 22, 2022
  
  be4bad6d
- using a string · a5a03925
  Davide Cieri authored Apr 22, 2022
  
  a5a03925
- echo · ea70f3c5
  Davide Cieri authored Apr 22, 2022
  
  ea70f3c5
- fixing loop · e479f793
  Davide Cieri authored Apr 22, 2022
  
  e479f793
- FEATURE: Adding recreate option to LaunchSimulation · 080020ee
  Davide Cieri authored Apr 22, 2022
  
  080020ee
- fixing yaml · d476496c
  Davide Cieri authored Apr 22, 2022
  
  d476496c
- exit 1 · 5fed694f
  Davide Cieri authored Apr 22, 2022
  
  5fed694f
- FEATURE: Adding check_timing CI job in collect stage, which checks if projects failed the timing. · 4140219c
  Davide Cieri authored Apr 22, 2022
  
  4140219c
Apr 14, 2022
- Merge remote-tracking branch 'origin/master' into 216-secondary-simulation-lib-shared_lib-conflict · 49dd0d87
  Davide Cieri authored Apr 14, 2022
  
  View commits for tag v6.8.0 v6.8.0
  
  49dd0d87
- FEATURE: Bugfix, setting the correct simset to recursive sim list files · 6946da6f
  Davide Cieri authored Apr 14, 2022
  
  View commit 6946da6f 2 tags
  
  6946da6f
- commenting debug · f6a906ff
  Davide Cieri authored Apr 14, 2022
  
  f6a906ff
- FEATURE: bugfix fixing problem with double-recursive sim list fiels · 7d947434
  Davide Cieri authored Apr 14, 2022
  
  7d947434
Apr 13, 2022
- xil_defaultlib is the default lib for verilog · 00ff6f7d
  Davide Cieri authored Apr 13, 2022
  
  View commits for tag v6.7.0 v6.7.0
  
  00ff6f7d
- FEATURE: fixing default properties for vh, svh and sv files · b740f0b2
  Davide Cieri authored Apr 13, 2022
  
  b740f0b2
Apr 11, 2022
- space · 23fdae18
  Davide Cieri authored Apr 11, 2022
  
  View commits for tag v6.6.0 v6.6.0
  
  23fdae18
- file tail · 1807ced0
  Davide Cieri authored Apr 11, 2022
  
  1807ced0
Apr 07, 2022
- FEATURE: Writing also the hierarchial utilization summary · 7c0dfdd2
  Davide Cieri authored Apr 07, 2022
  
  7c0dfdd2
- Hog must be sourced before using IsISE · 768880e3
  Davide Cieri authored Apr 07, 2022
  
  768880e3
- Merge remote-tracking branch 'origin/develop' into lib_for_verilog · 7888e536
  Davide Cieri authored Apr 07, 2022
  
  7888e536
- FEATURE: Restoring verilog property check · e53a2a16
  Davide Cieri authored Apr 07, 2022
  
  e53a2a16
- FEATURE: Fixing wave and do file settings. Fixing setting library with... · 64f5d84f
  Davide Cieri authored Apr 07, 2022
  64f5d84f
Apr 06, 2022
- removing default sim lib settings preventing setting of wavefiles · 6cd81d78
  Davide Cieri authored Apr 06, 2022
  
  6cd81d78
Apr 05, 2022
- fix call to IsXilinx · 427c8b5c
  Andrew Peck authored Apr 05, 2022
  
  View commits for tag v6.5.0 v6.5.0
  
  427c8b5c
- fix ide check for quartus · 407a0fe1
  Andrew Peck authored Apr 05, 2022
  
  407a0fe1
- implement commands to check ide version · a2796407
  Andrew Peck authored Apr 05, 2022
  
  a2796407
Apr 01, 2022
- FEATURE: add library also to verilog files · 1f14ecaa
  Francesco Gonnella authored Apr 01, 2022
  
  1f14ecaa
Mar 24, 2022
- silent curl · b77d409f
  Davide Cieri authored Mar 24, 2022
  
  View commits for tag v6.4.0 v6.4.0
  
  b77d409f
- silent xrdcp · ce9c4432
  Davide Cieri authored Mar 24, 2022
  
  ce9c4432
- again · 27800a81
  Davide Cieri authored Mar 24, 2022
  
  27800a81
- fix typo · 95f2da45
  Davide Cieri authored Mar 24, 2022
  
  95f2da45
- echo · f07f5ab4
  Davide Cieri authored Mar 24, 2022
  
  f07f5ab4
- fixing yaml · 97688427
  Davide Cieri authored Mar 24, 2022
  
  97688427
- let's try · 30dba33d
  Davide Cieri authored Mar 24, 2022
  
  30dba33d
- GetArtifactsAndRename does not take extra job artifacts if extracting doxygen · f7744ca4
  Davide Cieri authored Mar 24, 2022
  
  f7744ca4
- 7 everywhere · 91578727
  Davide Cieri authored Mar 24, 2022
  
  91578727
- FEATURE: Using 7-words SHA everywhere · b14aa9e2
  Davide Cieri authored Mar 24, 2022
  
  b14aa9e2