[go: up one dir, main page]

Kaur et al., 2022 - Google Patents

Enhanced chimp optimization algorithm for high level synthesis of digital filters

Kaur et al., 2022

View HTML
Document ID
4053219641776177751
Author
Kaur M
Kaur R
Singh N
Publication year
Publication venue
Scientific Reports

External Links

Snippet

The HLS of digital filters is a complex optimization task in electronic design automation that increases the level of abstraction for designing and scheming digital circuits. The complexity of this issue attracting the interest of the researcher and solution of this issue is a big …
Continue reading at www.nature.com (HTML) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3893Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30861Retrieval from the Internet, e.g. browsers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/78Architectures of general purpose stored programme computers comprising a single central processing unit
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N99/00Subject matter not provided for in other groups of this subclass
    • G06N99/005Learning machines, i.e. computer in which a programme is changed according to experience gained by the machine itself during a complete run
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F19/00Digital computing or data processing equipment or methods, specially adapted for specific applications
    • G06F19/10Bioinformatics, i.e. methods or systems for genetic or protein-related data processing in computational molecular biology
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06QDATA PROCESSING SYSTEMS OR METHODS, SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q10/00Administration; Management
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computer systems based on biological models
    • G06N3/12Computer systems based on biological models using genetic models
    • G06N3/126Genetic algorithms, i.e. information processing using digital simulations of the genetic system

Similar Documents

Publication Publication Date Title
Zhao et al. Optimizing CNN-based object detection algorithms on embedded FPGA platforms
Sekanina et al. Automated search-based functional approximation for digital circuits
Matsumoto et al. Distance-based clustering using QUBO formulations
Bruneel et al. Dynamic data folding with parameterizable FPGA configurations
Bondalapati et al. Reconfigurable computing: Architectures, models and algorithms
Goudarzi et al. Design of a universal logic block for fault-tolerant realization of any logic operation in trapped-ion quantum circuits
Takano et al. Design of a DSL for converting rust programming language into RTL
Bairamkulov et al. Graphs in vlsi circuits and systems
Kaur et al. Enhanced chimp optimization algorithm for high level synthesis of digital filters
Fricke et al. CGRA tool flow for fast run-time reconfiguration
Tetteh et al. Grammatical evolution of complex digital circuits in SystemVerilog
Pal et al. Machine learning for agile fpga design
Menard et al. High‐Level Synthesis under Fixed‐Point Accuracy Constraint
Kwon Machine Learning for AI-Augmented Design Space Exploration of Computer Systems
US8127259B2 (en) Synthesis constraint creating device, behavioral synthesis device, synthesis constraint creating method and recording medium
Mora et al. On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming
Leon-Vega et al. Automatic generation of resource and accuracy configurable processing elements
Jendrsczok et al. A scalable configurable architecture for the massively parallel GCA model
Kabir et al. A runtime programmable accelerator for convolutional and multilayer perceptron neural networks on fpga
Miyasaka et al. Sat-based mapping of data-flow graphs onto coarse-grained reconfigurable arrays
Iacca et al. Introducing kimeme, a novel platform for multi-disciplinary multi-objective optimization
Mami et al. A new HLS allocation algorithm for efficient DSP utilization in FPGAs
Kruppe et al. Efficient operator sharing modulo scheduling for sum-product network inference on fpgas
Andrianova et al. Hardware acceleration of statistical data processing based on FPGAs in corporate information systems
Grigoras et al. Dfesnippets: An open-source library for dataflow acceleration on FPGAs