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Kultala et al., 2017 - Google Patents

Exposed datapath optimizations for loop scheduling

Kultala et al., 2017

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Document ID
4535386089612671348
Author
Kultala H
Jääskeläinen P
IJzerman J
Lehtonen L
Viitanen T
Mäkitalo M
Takala J
Publication year
Publication venue
2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

External Links

Snippet

Transport Triggered Architecture (TTA) processors allow unique low level compiler optimizations such as software bypassing and operand sharing. Previously, these optimizations have mostly been performed inside single basic blocks, leaving much of their …
Continue reading at researchportal.tuni.fi (PDF) (other versions)

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