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Huang et al., 2016 - Google Patents

Timing-driven cell placement optimization for early slack histogram compression

Huang et al., 2016

View PDF
Document ID
5017145381668351353
Author
Huang C
Liu Y
Lu Y
Kuo Y
Chang Y
Kuo S
Publication year
Publication venue
Proceedings of the 53rd Annual Design Automation Conference

External Links

Snippet

As interconnects dominate circuit performance in modern chip designs, placement becomes an essential stage in optimizing timing. Recent timing-driven placement (TDP) techniques focus mainly on optimizing late slack rather than early slack. This paper presents a TDP …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

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    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G06F17/5031—Timing analysis
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    • G06F17/5072—Floorplanning, e.g. partitioning, placement
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    • G06F17/5077—Routing
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