[go: up one dir, main page]

Arunachalam et al., 2003 - Google Patents

Optimal shielding/spacing metrics for low power design

Arunachalam et al., 2003

View PDF
Document ID
541864979786572966
Author
Arunachalam R
Acar E
Nassif S
Publication year
Publication venue
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.

External Links

Snippet

Noise arising from line-to-line coupling is a major problem for deep submicron design, and present technology trends are causing an increase in this type of noise. Common current methods to decrease coupling noise include shielding and buffering, both of which can …
Continue reading at courses.ece.ubc.ca (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • G06F17/5031Timing analysis
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077Routing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072Floorplanning, e.g. partitioning, placement
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/82Noise analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/84Timing analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12Design for manufacturability

Similar Documents

Publication Publication Date Title
Arunachalam et al. Optimal shielding/spacing metrics for low power design
Kahng et al. On switch factor based analysis of coupled RC interconnects
Li et al. Architecture evaluation for power-efficient FPGAs
Sylvester et al. Impact of small process geometries on microarchitectures in systems on a chip
Kumar Interconnect and noise immunity design for the Pentium 4 processor
Alpert et al. Buffer insertion for noise and delay optimization
Shepard Design methodologies for noise in digital integrated circuits
US7549134B1 (en) Method and system for performing crosstalk analysis
JP3569681B2 (en) Method and apparatus for analyzing power supply current waveform in semiconductor integrated circuit
US7590958B2 (en) Method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities
Charbon et al. Modeling digital substrate noise injection in mixed-signal IC's
Kaul et al. Active shields: A new approach to shielding global wires
Bobba et al. IC power distribution challenges
US8056035B2 (en) Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing
Elgamel et al. Interconnect noise analysis and optimization in deep submicron technology
Ismail On-chip inductance cons and pros
Wolff Diffuse reflection (intensity reflectance model)
Coudert Timing and design closure in physical design flows
Heydari et al. Analysis and reduction of capacitive coupling noise in high-speed VLSI circuits
Pant et al. Static timing analysis considering power supply variations
Arunachalam et al. Page Paper title: Optimal Shielding/Spacing Metrics for Low Power Design
Okazaki et al. A multiple media delay simulator for MOS LSI circuits
Chen et al. New spare cell design for IR drop minimization in engineering change order
Mukherjee et al. Retiming and clock scheduling to minimize simultaneous switching
Mukherjee et al. Sizing power/ground meshes for clocking and computing circuit components