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Metzger et al., 2009 - Google Patents

Introspection mechanisms for runtime verification in a system-level design environment

Metzger et al., 2009

Document ID
5559011584518053232
Author
Metzger M
Anane A
Rousseau F
Vachon J
Aboulhamid E
Publication year
Publication venue
Microelectronics journal

External Links

Snippet

A new generation of computer-aided design (CAD) tools is mandatory to cope with the growing complexity of System-On-Chip. We believe that they should be built on top of a modern and standard framework. ESys. NET is a design environment based on the. NET …
Continue reading at www.sciencedirect.com (other versions)

Classifications

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    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • GPHYSICS
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    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
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    • G06F17/21Text processing
    • G06F17/22Manipulating or registering by use of codes, e.g. in sequence of text characters
    • G06F17/2247Tree structured documents; Markup, e.g. Standard Generalized Markup Language [SGML], Document Type Definition [DTD]
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    • G06QDATA PROCESSING SYSTEMS OR METHODS, SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES, NOT OTHERWISE PROVIDED FOR

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