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Ataei et al., 2016 - Google Patents

A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS

Ataei et al., 2016

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Document ID
5669352686902832792
Author
Ataei S
Stine J
Guthaus M
Publication year
Publication venue
2016 IEEE 34th international conference on computer design (ICCD)

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Snippet

In this paper, a novel differential single-port 12T SRAM bitcell is presented. This bitcell uses a read buffer to eliminate read disturbance, improves the read stability and achieves read static noise margin equal to its hold static noise margin. Using a column-based select signal …
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