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Salek et al., 1999 - Google Patents

An integrated logical and physical design flow for deep submicron circuits

Salek et al., 1999

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Document ID
5749963276737849359
Author
Salek A
Lou J
Pedram M
Publication year
Publication venue
IEEE transactions on computer-aided design of integrated circuits and systems

External Links

Snippet

This paper presents a set of techniques and a new design flow to be used in the synthesis of high-performance deep-submicron logic circuits. The design flow consists of circuit partitioning into tree like clusters, floorplanning, global routing, and timing …
Continue reading at www.mpedram.com (PDF) (other versions)

Classifications

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    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072—Floorplanning, e.g. partitioning, placement
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    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
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