Hauser et al., 2012 - Google Patents
Hierarchical model-order reduction for robust design of parameter-varying systemsHauser et al., 2012
- Document ID
- 582165268060689716
- Author
- Hauser M
- Salzig C
- Publication year
- Publication venue
- 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
External Links
Snippet
In this paper we introduce a robust method for the model-driven design of reduced parameter-varying analog systems. The ideas behind our approach are twofold: On the one hand we present an algorithm for decreasing the model order of large systems. It utilizes the …
- 230000001603 reducing 0 title abstract description 39
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
- G06F17/5031—Timing analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2839—Fault-finding or characterising using signal generators, power supplies or circuit analysers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B17/00—Systems involving the use of models or simulators of said systems
- G05B17/02—Systems involving the use of models or simulators of said systems electric
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105849570B (en) | Closed-loop simulation of computer models of physical systems and actual real-time hardware components | |
| Reis et al. | PABTEC: Passivity-preserving balanced truncation for electrical circuits | |
| US8726211B2 (en) | Generating an equivalent waveform model in static timing analysis | |
| CN109614687B (en) | Constant admittance modeling and real-time simulation method for two-level bridge converter | |
| Byeon et al. | A new DC offset removal algorithm using an iterative method for real-time simulation | |
| Wan et al. | Overview of commercially-available analog/RF simulation engines and design environment | |
| Farooq et al. | High level fault modeling and fault propagation in analog circuits using NLARX automated model generation technique | |
| Zhuang et al. | From Circuit Theory, Simulation to SPICE< sup> Diego<\/sup>: A Matrix Exponential Approach for Time-Domain Analysis of Large-Scale Circuits | |
| Tertel et al. | Real-time emulation of block-based analog circuits on an FPGA | |
| Steinhorst et al. | Equivalence checking of nonlinear analog circuits for hierarchical ams system verification | |
| Hauser et al. | Hierarchical model-order reduction for robust design of parameter-varying systems | |
| Ye et al. | Exact time-domain second-order adjoint-sensitivity computation for linear circuit analysis and optimization | |
| Gil et al. | SystemC AMS power electronic modeling with ideal instantaneous switches | |
| US9582622B1 (en) | Evaluating on-chip voltage regulation | |
| Tant et al. | Accurate second-order interpolation for power electronic circuit simulation | |
| US9697321B2 (en) | Method of identifying a value of an unknown circuit component in an analog circuit | |
| US8464195B1 (en) | Integrated circuit clock analysis with macro models | |
| US20120245904A1 (en) | Waveform-based digital gate modeling for timing analysis | |
| Szymanski et al. | A general common-bus architecture for multiple-interface power hardware-in-the-loop studies | |
| Fawaz et al. | Parallel simulation-based verification of RC power grids | |
| López-Colino et al. | Modeling of power converters for debugging digital controllers through FPGA emulation | |
| US11100268B1 (en) | Fast and accurate simulation for power delivery networks with integrated voltage regulators | |
| Fraccaroli et al. | Fault analysis in analog circuits through language manipulation and abstraction | |
| Shebaita et al. | A novel moment based framework for accurate and efficient static timing analysis | |
| Stakhiv et al. | Macromodeling as an alternative approach for electric power systems modeling using ATP and MATLAB/Simulink |