[go: up one dir, main page]

Zimpeck et al., 2020 - Google Patents

Circuit design using Schmitt Trigger to reliability improvement

Zimpeck et al., 2020

View PDF
Document ID
6355647075436441601
Author
Zimpeck A
Meinhardt C
Artola L
Hubert G
Kastensmidt F
Reis R
Publication year
Publication venue
Microelectronics Reliability

External Links

Snippet

This paper presents a design strategy to reduce the impact of process variations and soft error susceptibility in FinFET circuits. The mitigation is provided by connecting a Schmitt Trigger at the logic gate output. The improvements in power and delay variability can reach …
Continue reading at hal.science (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072Floorplanning, e.g. partitioning, placement
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12Design for manufacturability
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/0033Radiation hardening
    • H03K19/00338In field effect transistor circuits
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00323Delay compensation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application

Similar Documents

Publication Publication Date Title
Huang et al. A high performance SEU tolerant latch
Katsarou et al. Soft error interception latch: Double node charge sharing SEU tolerant design
Moghaddam et al. Design and evaluation of an efficient Schmitt trigger-based hardened latch in CNTFET technology
Qi et al. Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology
US9984192B2 (en) Cell having shifted boundary and boundary-shift scheme
Pown et al. Investigation of radiation hardened TFET SRAM cell for mitigation of single event upset
De Aguiar et al. Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology
Gupta et al. MCML D‐latch using triple‐tail cells: analysis and design
Badugu et al. Design of hardened flip-flop using Schmitt trigger-based SEM latch in CNTFET technology
Angeline et al. Design impacts of delay invariant high‐speed clock delayed dual keeper domino circuit
Aguiar et al. Radiation hardening efficiency of gate sizing and transistor stacking based on standard cells
Danilov et al. On board electronic devices safety provided by DICE-based Muller C-elements
Aguiar et al. Impact of complex logic cell layout on the single-event transient sensitivity
Yankang et al. Impact of pulse quenching effect on soft error vulnerabilities in combinational circuits based on standard cells
Vangal et al. Wide-range many-core SoC design in scaled CMOS: Challenges and opportunities
Zimpeck et al. Circuit-level hardening techniques to mitigate soft errors in FinFET logic gates
US11764765B2 (en) Aging-resistant Schmitt receiver circuit
Zimpeck et al. Circuit design using Schmitt Trigger to reliability improvement
Zimpeck et al. Mitigation of process variability effects using decoupling cells
Mahatme et al. An efficient technique to select logic nodes for single event transient pulse-width reduction
Zimpeck et al. Sleep transistors to improve the process variability and soft error susceptibility
Chen et al. Research and Improvement of Muller C Element
da Silva et al. Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology
Maroof et al. A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror
Zhao et al. A double-modules interlocking triple-node upset-tolerant latch design