Hülle et al., 2016 - Google Patents
SAT-ATPG for application-oriented FPGA testingHülle et al., 2016
View PDF- Document ID
- 6353950359956546168
- Author
- Hülle R
- Fišer P
- Schmidt J
- Borecký J
- Publication year
- Publication venue
- 2016 15th Biennial Baltic Electronics Conference (BEC)
External Links
Snippet
In this paper we propose a SAT-based ATPG algorithm for application-oriented FPGA testing. For this purpose, a novel fault model is introduced which combines the stuck-at fault model for interconnects testing with the bit-flip model for LUT testing. The concept of SAT …
- 101710003518 ATPAF2 0 abstract description 6
Classifications
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
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- G—PHYSICS
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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- G01R31/318385—Random or pseudo-random test pattern
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- G—PHYSICS
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- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
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- G—PHYSICS
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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