Knapp et al., 2002 - Google Patents
40 Gbit/s 2/sup 7/-1 PRBS generator IC in SiGe bipolar technologyKnapp et al., 2002
- Document ID
- 641689103070963654
- Author
- Knapp H
- Wurzer M
- Meister T
- Bock J
- Aufinger K
- Publication year
- Publication venue
- Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting
External Links
Snippet
A pseudo-random bit sequence (PRBS) generator with a sequence length of 2/sup 7/-1 is presented. The circuit is based on a linear feedback shift register operating at half the output data rate. It is manufactured in a pre-production SiGe bipolar technology with a cut-off …
- 229910000577 Silicon-germanium 0 title abstract description 8
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Pottbacker et al. | A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s | |
| Cao et al. | OC-192 transmitter and receiver in standard 0.18-/spl mu/m CMOS | |
| Farjad-Rad et al. | A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips | |
| Laskin et al. | A 60 mW per Lane, 4$, times, $23-Gb/s 2$^ 7-$1 PRBS Generator | |
| Hafez et al. | A 32–48 Gb/s serializing transmitter using multiphase serialization in 65 nm CMOS technology | |
| KR101184137B1 (en) | Clock transfer circuit and tester using the same | |
| Farjad-Rad et al. | A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os | |
| Momtaz et al. | A fully integrated SONET OC-48 transceiver in standard CMOS | |
| WO2007027833A2 (en) | Circuit, system, and method for multiplexing signals with reduced jitter | |
| Knapp et al. | 100-Gb/s 2/sup 7/-1 and 54-Gb/s 2/sup 11/-1 PRBS generators in SiGe bipolar technology | |
| KR20100023000A (en) | Resonant clock and interconnect architecture for digital devices with multiple clock networks | |
| Knapp et al. | 40 Gbit/s 2/sup 7/-1 PRBS generator IC in SiGe bipolar technology | |
| Dickson et al. | An 80-Gb/s 2/sup 31/-1 pseudorandom binary sequence generator in SiGe BiCMOS technology | |
| CN104467757B (en) | Clock pulse system, clock pulse integrated circuit and clock pulse generating method | |
| Byun et al. | A 10-Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector | |
| Hu et al. | A 15-Gb/s 0.0037-mm² 0.019-pJ/bit full-rate programmable multi-pattern pseudo-random binary sequence generator | |
| US6809567B1 (en) | System and method for multiple-phase clock generation | |
| Lee et al. | A 20Gb/s burst-mode CDR circuit using injection-locking technique | |
| Stout et al. | 10 Gb/s silicon bipolar 8: 1 multiplexer and 1: 8 demultiplexer | |
| Höppner et al. | An open-loop clock generator for fast frequency scaling in 65nm CMOS technology | |
| Dickson et al. | A 72 Gb/s 2/sup 31/-1 PRBS generator in SiGe BiCMOS technology | |
| Buttrick et al. | On testing prebond dies with incomplete clock networks in a 3d ic using dlls | |
| Meghelli | A 43-Gb/s full-rate clock transmitter in 0.18-/spl mu/m SiGe BiCMOS technology | |
| US8970267B2 (en) | Asynchronous clock dividers to reduce on-chip variations of clock timing | |
| US7567109B2 (en) | Integrated circuit devices generating a plurality of drowsy clock signals having different phases |