[go: up one dir, main page]

Richmond, 2000 - Google Patents

Successful implementation of structured testing

Richmond, 2000

Document ID
7408577543954559826
Author
Richmond R
Publication year
Publication venue
Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159)

External Links

Snippet

Successful implementation of structured testing Page 1 Successful Implementation of Structured Testing Ronald A. Richmond Texas Instruments, Inc. Dallas, TX Topics: Test Methods, Defect Signatures, Systematic Learning ABSTRACT This paper describes techniques …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31718Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30Marginal testing, e.g. varying supply voltage
    • G01R31/3004Current or voltage test
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2853Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302Contactless testing
    • G01R31/305Contactless testing using electron beams
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38Response verification devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006Current
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006Checking stores for correct operation; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. WSI

Similar Documents

Publication Publication Date Title
US6943575B2 (en) Method, circuit and system for determining burn-in reliability from wafer level burn-in
US5666049A (en) Semiconductor testing apparatus, semiconductor testing circuit chip, and probe card
US6587980B2 (en) Intelligent binning for electrically repairable semiconductor chips
Nigh et al. Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
Henry et al. Burn-in elimination of a high volume microprocessor using I/sub DDQ
Righter et al. CMOS IC reliability indicators and burn-in economics
CN101738400B (en) Method and device for judging repeated defects on surface of wafer
Richmond Successful implementation of structured testing
KR20060019556A (en) Integrated circuit device test method and apparatus, integrated circuit device
Gayle The cost of quality: Reducing ASIC defects with I/sub DDQ/, at-speed testing, and increased fault coverage
JPH11213695A (en) Semiconductor memory-testing device
Madge et al. The value of statistical testing for quality, yield and test cost improvement
Butler et al. Successful development and implementation of statistical outlier techniques on 90nm and 65nm process driver devices
US7284213B2 (en) Defect analysis using a yield vehicle
US11131711B1 (en) Testing system and method for in chip decoupling capacitor circuits
Tsujide et al. Automatic memory failure analysis using an expert system in conjunction with a memory tester/analyzer
Balachandran et al. Improvement of SRAM-based failure analysis using calibrated Iddq testing
Ahuja et al. Intel386 EX embedded processor I/sub DDQ/testing
Arnold et al. Test methods used to produce highly reliable known good die (KGD)
Peterson et al. Practical application of energy consumption ratio test
Jiang et al. Performance comparison of VLV, ULV, and ECR tests
CN100388453C (en) semiconductor defect detection method and system
Crouch et al. Processing high volume scan test results for yield learning
Benware Achieving sub 100 DPPM defect levels on VDSM and nanometer ASICs
Karthikeyan et al. 32nm yield learning using addressable defect arrays