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Bouvry et al., 1994 - Google Patents

Mapping and load balancing on distributed memory systems

Bouvry et al., 1994

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Document ID
7536982219966663155
Author
Bouvry P
Chassin J
Dobrucky M
Hluchy L
Luque E
Margalef T
Publication year
Publication venue
Proceedings of the Eight Symposium on Microcomputer and Microprocessor Applications

External Links

Snippet

Two kinds of tools are necessary to optimise the use of available resources by the execution of parallel programs on distributed memory systems: mapping and load balancing tools. A mapping tool is well suited for programs whose behaviour is predictable while for many" real …
Continue reading at www.academia.edu (PDF) (other versions)

Classifications

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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
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    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
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    • G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
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