Schliebusch et al., 2005 - Google Patents
A framework for automated and optimized ASIP implementation supporting multiple hardware description languagesSchliebusch et al., 2005
View PDF- Document ID
- 755432149360304640
- Author
- Schliebusch O
- Chattopadhyay A
- Kammler D
- Ascheid G
- Leupers R
- Meyr H
- Kogel T
- Publication year
- Publication venue
- Proceedings of the 2005 Asia and South Pacific Design Automation Conference
External Links
Snippet
Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design space exploration is well supported by numerous tools providing high flexibility and quality …
- 102000006822 Agouti Signaling Protein 0 title abstract 2
Classifications
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- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
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- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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- G06F17/504—Formal methods
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- G06F17/5022—Logic simulation, e.g. for logic circuit operation
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- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
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- G06F17/5077—Routing
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- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
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- G—PHYSICS
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
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- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
- G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
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