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Lira et al., 2013 - Google Patents

Replacement techniques for dynamic NUCA cache designs on CMPs

Lira et al., 2013

Document ID
7899810885145518521
Author
Lira J
Molina C
Rakvic R
González A
Publication year
Publication venue
The Journal of Supercomputing

External Links

Snippet

The growing influence of wire delay in cache design has meant that access latencies to last- level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have been proposed to address this problem. Furthermore, an efficient last-level cache is crucial …
Continue reading at link.springer.com (other versions)

Classifications

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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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