[go: up one dir, main page]

Julio et al., 2015 - Google Patents

Energy-efficient Gaussian filter for image processing using approximate adder circuits

Julio et al., 2015

View PDF
Document ID
7963327770779261109
Author
Julio R
Soares L
Costa E
Bampi S
Publication year
Publication venue
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

External Links

Snippet

This paper proposes the use of approximate adder circuits for 3× 3 and 5× 5 Gaussian filter implementations. The Gaussian filter is a convolution operator which is used to blur images and to remove noise, whose convolution implementation can be designed in hardware …
Continue reading at 2024.sci-hub.box (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding, overflow
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/16—Constructional details or arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/388—Skewing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks

Similar Documents

Publication Publication Date Title
Julio et al. Energy-efficient Gaussian filter for image processing using approximate adder circuits
Ullah et al. Area-optimized accurate and approximate softcore signed multiplier architectures
Zendegani et al. RoBA multiplier: A rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing
Van et al. Generalized low-error area-efficient fixed-width multipliers
Esposito et al. On the use of approximate adders in carry-save multiplier-accumulators
Venkatachalam et al. Approximate sum-of-products designs based on distributed arithmetic
Kumar et al. Design and performance analysis of Multiply-Accumulate (MAC) unit
Mukherjee et al. Counter based low power, low latency Wallace tree multiplier using GDI technique for on-chip digital filter applications
Wang et al. Approximate multiply-accumulate array for convolutional neural networks on fpga
Tomar et al. Modified binary multiplier architecture to achieve reduced latency and hardware utilization
Chiranjeevi et al. Pipeline Architecture for N= K* 2 L Bit Modular ALU: Case Study between Current Generation Computing and Vedic Computing
Sudha et al. A novel method for computing exponential function using cordic algorithm
de Oliveira et al. Exploiting approximate adder circuits for power-efficient Gaussian and Gradient filters for Canny edge detector algorithm
Sakellariou et al. Application-specific low-power multipliers
Kumar et al. Complex multiplier: implementation using efficient algorithms for signal processing application
Koshita et al. High-accuracy and area-efficient stochastic FIR digital filters based on hybrid computation
Kang et al. Novel approximate synthesis flow for energy-efficient FIR filter
KR101878400B1 (en) FIR filter calculation method using approximate synthesis
Thamizharasan et al. An efficient VLSI architecture for FIR filter using computation sharing multiplier
Ranjbar et al. FPGA-Based Multiplier with a New Approximate Full Adder for Error-Resilient Applications
Guo et al. Truncated MCM using pattern modification for FIR filter implementation
Yeary et al. Theory and implementation of a computationally efficient decimation filter for power-aware embedded systems
Zhang et al. Multiplier-less VLSI architecture for real-time computation of multi-dimensional convolution
Varalakshmi et al. Implementation of Multiplier Architecture Using Efficientcarry Select Adders for Synthesizing Fir Filters
Gari et al. VLSI Architecture of High Throughput Processing Unit for Efficiently Executing 2D Convolution for Deep Neural Network based Applications