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Bethur et al., 2023 - Google Patents

Hier-3D: A methodology for physical hierarchy exploration of 3-D ICs

Bethur et al., 2023

Document ID
8178353546198550477
Author
Bethur N
Agnesina A
Brunion M
Garcia-Ortiz A
Catthoor F
Milojevic D
Komalan M
Cavalcante M
Riedel S
Benini L
Lim S
Publication year
Publication venue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

External Links

Snippet

Hierarchical very-large-scale integration (VLSI) flows are an understudied yet critical approach to achieving design closure at giga-scale complexity and gigahertz frequency targets. This article proposes a novel hierarchical physical design flow enabling the building …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072—Floorplanning, e.g. partitioning, placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077—Routing
    • G—PHYSICS
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    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
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    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
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