Clermidy et al., 2009 - Google Patents
A communication and configuration controller for noc based reconfigurable data flow architectureClermidy et al., 2009
- Document ID
- 8433122684542167223
- Author
- Clermidy F
- Lemaire R
- Thonnart Y
- Vivet P
- Publication year
- Publication venue
- 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
External Links
Snippet
While network-on-chip aspects such as topologies, routing strategies or quality-of-service have been largely studied, the mapping of real applications on distributed NoC-based architecture is still an open issue. In this paper, we address this issue for complex …
- 238000004891 communication 0 title abstract description 28
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogramme communication; Intertask communication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/44—Arrangements for executing specific programmes
- G06F9/455—Emulation; Software simulation, i.e. virtualisation or emulation of application or operating system execution engines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5693—Queue scheduling in packet switching networks
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100557594C (en) | State Engine for Data Processors | |
| Karam et al. | Trends in multicore DSP platforms | |
| JP6096120B2 (en) | Load / store circuitry for processing clusters | |
| US11012411B2 (en) | Network interface device | |
| Hansson et al. | Trade-offs in the configuration of a network on chip for multiple use-cases | |
| US7996581B2 (en) | DMA engine | |
| US6330584B1 (en) | Systems and methods for multi-tasking, resource sharing and execution of computer instructions | |
| US20100088703A1 (en) | Multi-core system with central transaction control | |
| CN116661870A (en) | RISC-V architecture-based high-performance embedded processor | |
| US11281506B2 (en) | Virtualised gateways | |
| CN109450705B (en) | A mapping-oriented network-on-chip verification method and system based on FPGA | |
| WO2019090247A1 (en) | Network system including match processing unit for table-based actions | |
| CN105359098A (en) | Dynamic Reconfiguration of Applications on Multiprocessor Embedded Systems | |
| CA3167334A1 (en) | Zero packet loss upgrade of an io device | |
| US11507378B1 (en) | Hardware engine with configurable instructions | |
| US7733771B2 (en) | NoC semi-automatic communication architecture for “data flows” applications | |
| US11762661B2 (en) | Counter for preventing completion of a thread including a non-blocking external device call with no-return indication | |
| Clermidy et al. | A communication and configuration controller for noc based reconfigurable data flow architecture | |
| Contini et al. | Enabling reconfigurable HPC through MPI-based inter-FPGA communication | |
| JP2013058200A (en) | Processor for message-based network interface using speculative techniques | |
| US10853077B2 (en) | Handling Instruction Data and Shared resources in a Processor Having an Architecture Including a Pre-Execution Pipeline and a Resource and a Resource Tracker Circuit Based on Credit Availability | |
| Wang et al. | Efficient support of AXI4 transaction ordering requirements in many-core architecture | |
| US20050281202A1 (en) | Monitoring instructions queueing messages | |
| Li et al. | DRA: Ultra-Low Latency Network I/O for TSN Embedded End-Systems | |
| Gao | Collective Communication Enabled Transformer Acceleration on Heterogeneous Clusters |