[go: up one dir, main page]

Tiwari et al., 2017 - Google Patents

Power gating technique for reducing leakage power in digital asynchronous GasP circuits

Tiwari et al., 2017

View PDF
Document ID
8475853670606380486
Author
Tiwari R
Ranjan R
Baig M
Sravya E
Publication year
Publication venue
2017 International Conference on Inventive Computing and Informatics (ICICI)

External Links

Snippet

There are multiple methods to reduce power consumption of digital circuits one of them is power gating. This paper introduces a new Power Gating technique for the GasP family of asynchronous circuits to achieve power savings. Large amount of power utilization in digital …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction for memory cells of the field-effect type
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0016Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/012Modifications of generator to improve response time or to decrease power consumption
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096Synchronous circuits, i.e. using clock signals
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BINDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B60/00Information and communication technologies [ICT] aiming at the reduction of own energy use
    • Y02B60/10Energy efficient computing
    • Y02B60/12Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply
    • Y02B60/1278Power management
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Similar Documents

Publication Publication Date Title
US7977972B2 (en) Ultra-low power multi-threshold asynchronous circuit design
US7652513B2 (en) Slave latch controlled retention flop with lower leakage and higher performance
US8456214B2 (en) State retention circuit and method of operation of such a circuit
Usami et al. Automated selective multi-threshold design for ultra-low standby applications
US7511535B2 (en) Fine-grained power management of synchronous and asynchronous datapath circuits
CN101777907A (en) Low-power dissipation RS latch unit and low-power dissipation master-slave D flip-flop
Shanmugasundaram Clock gating techniques: an overview
Consoli et al. Novel class of energy-efficient very high-speed conditional push–pull pulsed latches
Kang Elements of low power design for integrated systems
Tiwari et al. Power gating technique for reducing leakage power in digital asynchronous GasP circuits
Shiny et al. Integration of clock gating and power gating in digital circuits
Kalyani et al. Various low power techniques for CMOS circuits
Sedighiani et al. A 380 fW leakage data retention flip-flop for short sleep periods
Balan et al. Dual-edge triggered sense-amplifier flip-flop for Low Power systems
CET Review of low power design techniques for flip-flops
Maheshwari A Comparative Analysis for Low-voltage, Low-power, and Low-energy Flip-flops
Banga et al. Implementation of 16× 16 SRAM memory array
Li et al. Power efficient data retention logic design in the integration of power gating and clock gating
Sheng et al. Leakage minimization of single-phase register file based on two-phase CPAL using MTCMOS
Nakabayashi et al. Low power semi-static TSPC D-FFs using split-output latch
Devlin et al. Energy minimum operation with self synchronous gate-level autonomous power gating and voltage scaling
Padwal Just-In-Time Power Gating of GasP Circuits
Tiwari et al. Low Power GasP Circuits using Power Gating
Mann et al. Power Gated ECRL Adiabatic Logic Based Optimized Two-Input Multiplexer
Patel et al. Low power SOC design Techniques