[go: up one dir, main page]

Wang et al., 2023 - Google Patents

A 1.6 GS/s 42.6-dB SNDR synthesis friendly time-interleaved SAR ADC using metastability detection and escape acceleration technique

Wang et al., 2023

Document ID
8908740810133616480
Author
Wang J
Gao Z
Cheng X
Wang J
Li Z
Han J
Zeng X
Publication year
Publication venue
IEEE Transactions on Circuits and Systems II: Express Briefs

External Links

Snippet

This brief proposes a metastability detection and escape acceleration (MDEA) technique to enhance the bandwidth and lower the switching power of successive-approximation register (SAR) analog-to-digital converters (ADCs). It is implemented as an AC-coupling switched …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/34Analogue value compared with reference values
    • H03M1/38Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/34Analogue value compared with reference values
    • H03M1/36Analogue value compared with reference values simultaneously only, i.e. parallel type
    • H03M1/361Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
    • H03M1/362Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
    • H03M1/365Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/0678Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
    • H03M1/068Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
    • H03M1/0682Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0634Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
    • H03M1/0656Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain
    • H03M1/066Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain by continuously permuting the elements used, i.e. dynamic element matching
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/34Analogue value compared with reference values
    • H03M1/38Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/40Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
    • H03M1/403Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type using switched capacitors
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/14Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/145Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/74Simultaneous conversion
    • H03M1/80Simultaneous conversion using weighted impedances
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/68Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H03M1/682Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits both converters being of the unary decoded type
    • H03M1/685Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits both converters being of the unary decoded type the quantisation value generators of both converters being arranged in a common two-dimensional array
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/74Simultaneous conversion
    • H03M1/742Simultaneous conversion using current sources as quantisation value generators
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00Conversion of analogue values to or from differential modulation
    • H03M3/30Delta-sigma modulation
    • H03M3/39Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/438Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
    • H03M3/454Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/1205Multiplexed conversion systems
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/662Multiplexed conversion systems
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0614Continuously compensating for, or preventing, undesired influence of physical parameters of harmonic distortion
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/004Reconfigurable analogue/digital or digital/analogue converters
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10Calibration or testing
    • H03M1/1009Calibration

Similar Documents

Publication Publication Date Title
Liu et al. A 12b 22.5/45MS/s 3.0 mW 0.059 mm 2 CMOS SAR ADC achieving over 90dB SFDR
Zhou et al. A 12 bit 160 MS/s two-step SAR ADC with background bit-weight calibration using a time-domain proximity detector
KR101512098B1 (en) SAR ADC using C-R hybrid DAC
Lyu et al. A 4-GS/s 39.9-dB SNDR 11.7-mW hybrid voltage-time two-step ADC with feedforward ring oscillator-based TDCs
Li et al. A 7-bit 3.8-GS/s 2-way time-interleaved 4-bit/cycle SAR ADC 16× time-domain interpolation in 28-nm CMOS
AlMarashli et al. A Nyquist rate SAR ADC employing incremental sigma delta DAC achieving peak SFDR= 107 dB at 80 kS/s
Wang et al. A 1.6 GS/s 42.6-dB SNDR synthesis friendly time-interleaved SAR ADC using metastability detection and escape acceleration technique
Tsai et al. An 8 b 700 MS/s 1 b/cycle SAR ADC using a delay-shift technique
Cenci et al. A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator
Li et al. High-resolution and high-speed integrated cmos ad converters for low-power applications
Wang et al. A 0.5 V 10-bit SAR ADC with offset calibrated time-domain comparator
Kumar et al. A 6-bit, 29.56 fJ/conv-step, voltage scalable Flash-SAR hybrid ADC in 28 nm CMOS
Xie et al. A 12bit 16MS/s Asynchronous SAR ADC with Speed-Enhanced Comparator and TSPC Latch
Yonar et al. An 8b 1.0-to-1.25 GS/s time-based ADC with bipolar VTC and sense amplifier latch interpolated gated ring oscillator TDC
Liang et al. A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS
Xing et al. A 0.021 mm 2 92dB-SNDR 88kHz-BW Incremental Zoom ADC with 2 nd-order RT-DEM and Quiet Chopping
AlMarashli et al. A hybrid comparator for high resolution SAR ADC
Du et al. A 10-bit 100MS/s subrange SAR ADC with time-domain quantization
Dong et al. An 11.36-Bit 405 μW SAR-VCO ADC with single-path differential VCO-based quantizer in 65 nm CMOS
Meng et al. A 1.8-GS/s 6-bit two-step sar ADC in 65-NM CMOS
Hu et al. A 12.5-fJ/conversion-step 8-bit 800-MS/s two-step SAR ADC
Hou et al. A 12-bit 50MS/s SAR ADC with non-binary split capacitive DAC in 40nm CMOS
Zhong et al. A 25 MHz-BW 81 dB-DR TDC-Based CTDSM With Background Analog-Integration-Based ISI Error Calibration Achieving> 8 dB Even-Order Harmonic Suppression
Campos et al. Design of a low power 10-bit 12MS/s asynchronous SAR ADC in 65nm CMOS
Wu et al. A 7 bit 800MS/S SAR ADC with background offset calibration