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Wang et al., 2007 - Google Patents

The design-for-testability features of a general purpose microprocessor

Wang et al., 2007

Document ID
9092722942545873900
Author
Wang D
Fan X
Fu X
Liu H
Wen K
Li R
Li H
Hu Y
Li X
Publication year
Publication venue
2007 IEEE International Test Conference

External Links

Snippet

This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. Major DFT solutions are implemented …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555Control logic
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    • G01R31/318572Input/Output interfaces
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    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536Scan chain arrangements, e.g. connections, test bus, analog signals
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    • G01R31/318594Timing aspects
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    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • G01R31/318558Addressing or selecting of subparts of the device under test
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    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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    • G01R31/318577AC testing, e.g. current testing, burn-in
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    • G01R31/318575Power distribution; Power saving
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    • G01R31/318583Design for test
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    • G01R31/319Tester hardware, i.e. output processing circuit
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3177Testing of logic operation, e.g. by logic analysers
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    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
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    • G01R31/31725Timing aspects, e.g. clock distribution, skew, propagation delay
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    • G01MEASURING; TESTING
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14Implementation of control logic, e.g. test mode decoders

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