Ma, 1995 - Google Patents
Testing BiCMOS and dynamic CMOS logicMa, 1995
View PS- Document ID
- 9159285881286001816
- Author
- Ma S
- Publication year
External Links
Snippet
In a normal integrated circuit (IC) production cycle, manufactured ICs are tested to remove defective parts. The purpose of this research is to study the effects of real defects in BiCMOS and dynamic CMOS circuits, and propose better test solutions to detect these defects …
- 230000000694 effects 0 abstract description 39
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318594—Timing aspects
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. varying supply voltage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Hawkins et al. | Defect classes-an overdue paradigm for CMOS IC testing | |
| Mourad et al. | Principles of testing electronic systems | |
| Ferguson et al. | Testing for parametric faults in static CMOS circuits | |
| Lala | Digital circuit testing and testability | |
| Acken | Deriving accurate fault models | |
| Greenstein et al. | E-PROOFS: a CMOS bridging fault simulator | |
| Vierhaus et al. | CMOS bridges and resistive transistor faults: IDDQ versus delay effects | |
| Gulati et al. | IDDQ testing of VLSI circuits | |
| Li et al. | Diagnosis of sequence-dependent chips | |
| Lee et al. | Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults | |
| Li et al. | Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs | |
| Franco et al. | Three-pattern tests for delay faults | |
| Bose et al. | A fault simulator for MOS LSI circuits | |
| Kundu et al. | Test challenges in nanometer technologies | |
| CN113514751B (en) | System and method for identifying integrated circuit defects and computer readable storage medium | |
| Ma | Testing BiCMOS and dynamic CMOS logic | |
| Konuk et al. | Charge-based fault simulation for CMOS network breaks | |
| Nigh | Built-in current testing | |
| Chen et al. | Improving Efficiency of Cell-Aware Fault Modeling By Utilizing Defect-Free Analog Simulation | |
| Yang | Simulation of faults causing analog behavior in digital circuits | |
| Ma et al. | Center for Reliable Computing | |
| Konuk et al. | Accurate and efficient fault simulation of realistic CMOS network breaks | |
| Lee et al. | BIFEST: A built-in intermediate fault effect sensing and test generation system for CMOS bridging faults | |
| Chang | Voltage screens for early-life failures in CMOS integrated circuits | |
| Stewart et al. | BiCMOS defect-modelling and fault analysis |