[go: up one dir, main page]

Pointner et al., 2019 - Google Patents

Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows

Pointner et al., 2019

Document ID
931101976525821687
Author
Pointner S
Frank O
Hazott C
Wille R
Publication year
Publication venue
2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

External Links

Snippet

The ever increasing complexity of modern circuits and systems remains a big challenge for the semiconductor industry. Since the life cycle of new products is getting smaller and smaller, companies have to speed-up their design flows to stay competitive. This particularly …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318385—Random or pseudo-random test pattern
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuit
    • G01R31/31903—Tester hardware, i.e. output processing circuit tester configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. varying supply voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2733—Test interface between tester and unit under test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING STRUCTURES OR APPARATUS NOT OTHERWISE PROVIDED FOR
    • G01M7/00—Vibration-testing of structures; Shock-testing of structures
    • G01M7/08—Shock-testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression

Similar Documents

Publication Publication Date Title
Ziade et al. A survey on fault injection techniques
KR100491461B1 (en) METHOD AND APPARATUS FOR SoC DESIGN VALIDATION
US9262303B2 (en) Automated semiconductor design flaw detection system
KR100463735B1 (en) Method for design validation of complex ic
KR100936855B1 (en) Manufacturing method and apparatus to avoid prototype-hold in asic/soc manufacturing
US7356786B2 (en) Method and user interface for debugging an electronic system
US6581191B1 (en) Hardware debugging in a hardware description language
US20050193280A1 (en) Design instrumentation circuitry
US20060195822A1 (en) Method and system for debugging an electronic system
Civera et al. Exploiting FPGA for accelerating fault injection experiments
Vermeulen et al. Test and debug strategy of the PNX8525 Nexperia/sup TM/digital video platform system chip
KR20040007463A (en) Method and apparatus for design validation of complex ic without using logic simulation
Abdelatty et al. Fault: Open-source eda’s missing dft toolchain
Pointner et al. Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows
JP4213306B2 (en) Program debugging device for semiconductor testing
Mohamed Pre-silicon verification and post-silicon validation methodologies
Pointner et al. Test Your Test Programs Pre-Silicon
Kakoee et al. Enhancing the testability of RTL designs using efficiently synthesized assertions
Aderholz et al. Virtual Test Development Using Pre-Silicon Verification Environment
Siripokarpirom et al. Hardware-assisted simulation and evaluation of IP cores using FPGA-based rapid prototyping boards
Nirmaier et al. Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification
Chakravarthi SOC Design Verification
US20240232485A1 (en) Test point insertion in analog circuit design testing
Das et al. Implementation of a testing environment for digital IP cores
Perkins et al. VTest program mixed-signal virtual test approach