[go: up one dir, main page]

Lahiri et al., 2006 - Google Patents

The LOTTERYBUS on-chip communication architecture

Lahiri et al., 2006

View PDF
Document ID
9536963327316983253
Author
Lahiri K
Raghunathan A
Lakshminarayana G
Publication year
Publication venue
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

External Links

Snippet

On-chip communication architectures play an important role in determining the overall performance of System-on-Chip (SoC) designs. Communication architectures should be flexible so as to offer high performance over a wide range of traffic characteristics. In …
Continue reading at scholar.archive.org (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4887—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues involving deadlines, e.g. rate based, periodic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/86—Hardware-Software co-design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes

Similar Documents

Publication Publication Date Title
Lahiri et al. The LOTTERYBUS on-chip communication architecture
Lahiri et al. LOTTERYBUS: A new high-performance communication architecture for system-on-chip designs
US6877053B2 (en) High performance communication architecture for circuit designs using probabilistic allocation of resources
Lahiri et al. Design space exploration for optimizing on-chip communication architectures
Lahiri et al. Evaluation of the traffic-performance characteristics of system-on-chip communication architectures
Hu et al. System-level buffer allocation for application-specific networks-on-chip router design
Poletti et al. Performance analysis of arbitration policies for SoC communication architectures
Pande et al. Performance evaluation and design trade-offs for network-on-chip interconnect architectures
Tran et al. Achieving high-performance on-chip networks with shared-buffer routers
Ascia et al. Multi-objective mapping for mesh-based NoC architectures
Narayan et al. Synthesis of system-level bus interfaces
Pasricha et al. Constraint-driven bus matrix synthesis for MPSoC
Shrivastava et al. Various arbitration algorithm for on-chip (AMBA) shared bus multi-processor SoC
Lahiri et al. Design of high-performance system-on-chips using communication architecture tuners
Shanthi et al. Design of efficient on-chip communication architecture in MpSoC
Shanthi et al. Performance analysis of on-chip communication architecture in MPSoC
Khanam et al. Design a low latency Arbiter for on chip Communication Architecture
Gomony et al. Coupling tdm noc and dram controller for cost and performance optimization of real-time systems
Pasricha et al. A framework for cosynthesis of memory and communication architectures for MPSoC
Yan et al. Centralized priority management allocation for network-on-chip router
Hwang et al. Implementation of a self-motivated arbitration scheme for the multilayer AHB busmatrix
Doifode et al. Dynamic lottery bus arbiter for shared bus system on chip: a design approach with VHDL
Zitouni et al. Communication architecture synthesis for multi-bus SoC
Lahiri On-chip communication: system-level architectures and design methodologies
Madsen et al. Network-centric system-level model for multiprocessor soc simulation