[go: up one dir, main page]

Gettings et al., 2008 - Google Patents

Study of CMOS process variation by multiplexing analog characteristics

Gettings et al., 2008

View PDF
Document ID
9552198449348059294
Author
Gettings K
Boning D
Publication year
Publication venue
IEEE transactions on Semiconductor Manufacturing

External Links

Snippet

Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic capacitance must be carefully modeled for accurate circuit …
Continue reading at dspace.mit.edu (PDF) (other versions)

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequence
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30Marginal testing, e.g. varying supply voltage
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832Specific tests of electronic circuits not provided for elsewhere
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Similar Documents

Publication Publication Date Title
Orshansky et al. Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits
Bhushan et al. Microelectronic test structures for CMOS technology
Zhao et al. Rigorous extraction of process variations for 65-nm CMOS design
Andraud et al. One-shot non-intrusive calibration against process variations for analog/RF circuits
Chen et al. An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution
Huynh et al. Automatic analog test signal generation using multifrequency analysis
Ketchen et al. High speed test structures for in-line process monitoring and model calibration [CMOS applications]
Abdallah et al. RF front-end test using built-in sensors
Bhushan et al. CMOS test and evaluation
US20100037191A1 (en) Method of generating reliability verification library for electromigration
Koneru et al. Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testing
Sauter et al. Effect of parameter variations at chip and wafer level on clock skews
Orshansky et al. Direct sampling methodology for statistical analysis of scaled CMOS technologies
Gettings et al. Study of CMOS process variation by multiplexing analog characteristics
CN108038322B (en) Modeling method and system of SPICE (simulation program with Integrated Circuit emphasis) centralized model
Jacomet FANTESTIC: Towards a powerful fault analysis and test pattern generator for integrated circuits
Doong et al. Field-configurable test structure array (FC-TSA): Enabling design for monitor, model, and manufacturability
CN109473367B (en) MOS capacitor test structure in SOI process and implementation method thereof
Saxena et al. Test structures and analysis techniques for estimation of the impact of layout on MOSFET performance and variability
Arora et al. Interconnect characterization of X architecture diagonal lines for VLSI design
JP4060516B2 (en) Parameter extraction method, parameter extraction apparatus, and circuit simulation system for circuit simulation
CN115332228A (en) System and method for testing MOS device
Zhang et al. All regimes parasitic capacitances extraction using a multi-channel CBCM technique
Nouet et al. Use of test structures for characterization and modeling of inter-and intra-layer capacitances in a CMOS process
Chan et al. Design dependent process monitoring for back-end manufacturing cost reduction