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Lotfi-Kamran et al., 2008 - Google Patents

Stall power reduction in pipelined architecture processors

Lotfi-Kamran et al., 2008

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Document ID
9681141943609861459
Author
Lotfi-Kamran P
Rahmani A
Salehpour A
Afzali-Kusha A
Navabi Z
Publication year
Publication venue
21st International Conference on VLSI Design (VLSID 2008)

External Links

Snippet

This paper proposes a technique for dynamic power reduction of pipelined processors. Pipelined processors frequently insert NOP instruction to the pipe for generating delay or resolving dependency. Our study shows that the percentage of power consumed by NOP …
Continue reading at cs.ipm.ac.ir (PDF) (other versions)

Classifications

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    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
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    • G06F1/32—Means for saving power
    • G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234—Action, measure or step performed to reduce power consumption
    • G06F1/3237—Power saving by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
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    • G06F9/3842—Speculative instruction execution
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    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
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    • G—PHYSICS
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    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
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    • G—PHYSICS
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    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G—PHYSICS
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