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Cutaia et al., 2015 - Google Patents

Fabrication and analysis of vertical p-type InAs-Si nanowire Tunnel FETs

Cutaia et al., 2015

Document ID
9750119904033581164
Author
Cutaia D
Moselund K
Borg M
Schmid H
Gignac L
Breslin C
Karg S
Uccelli E
Nirmalraj P
Riel H
Publication year
Publication venue
EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon

External Links

Snippet

We report InAs-Si nanowire (NW) Tunnel FETs fabricated inside nanotube templates. High device yield and performances are obtained by optimizing the growth conditions and the fabrication flow using inorganic material as dielectric spacer, atomic-layer-deposition for the …
Continue reading at ieeexplore.ieee.org (other versions)

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