[go: up one dir, main page]

Jeong et al., 2006 - Google Patents

Optimal technology mapping and cell merger for asynchronous threshold networks

Jeong et al., 2006

View PS
Document ID
1150378117756566290
Author
Jeong C
Nowick S
Publication year
Publication venue
12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)

External Links

Snippet

A key challenge in using robust asynchronous circuit styles is the lack of powerful automated optimization techniques. In this paper, optimal technology mapping and cell merger algorithms for robust asynchronous threshold networks are introduced. The technology …
Continue reading at www.cs.columbia.edu (PS) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/504Formal methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

Similar Documents

Publication Publication Date Title
Chatterjee et al. Reducing structural bias in technology mapping
US7900173B1 (en) Temporal decomposition for design and verification
Vemuri et al. BDD-based logic synthesis for LUT-based FPGAs
JP4000567B2 (en) Efficient bounded model checking method
Teubner et al. Data processing on FPGAs
EP1964266B1 (en) A method for multi-cycle clock gating
Baumgartner et al. Scalable sequential equivalence checking across arbitrary design transformations
Jeong et al. Optimization of robust asynchronous circuits by local input completeness relaxation
Parsan et al. Gate mapping automation for asynchronous NULL convention logic circuits
Kuehlmann et al. Transformation-based verification using generalized retiming
US7840915B2 (en) Methods and media for forming a bound network
Jeong et al. Technology mapping and cell merger for asynchronous threshold networks
Dashkin et al. General approach to asynchronous circuits simulation using synchronous fpgas
Jain et al. A survey of techniques for formal verification of combinational circuits
Jeong et al. Optimal technology mapping and cell merger for asynchronous threshold networks
Lavagno et al. Synthesis of verifiably hazard-free asynchronous control circuits
Kishinevsky et al. Partial-scan delay fault testing of asynchronous circuits
Serre et al. DSL-based hardware generation with scala: Example fast Fourier transforms and sorting networks
Sklyarov et al. Hardware implementations of software programs based on hierarchical finite state machine models
Ammes et al. Two-level and multilevel approximate logic synthesis
Stahl et al. Hazard detection in a GALS wrapper: A case study
Mokhov Algebra of switching networks
EP1515251B1 (en) Efficient approaches for bounded model checking
Jacobi A study of the application of binary decision diagrams in multilevel logic synthesis
Jeong et al. Technology Mapping for Robust Asynchronous Threshold Networks