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CHEN, 2024 - Google Patents

Compiling OpenMP task graphs to parallel hardware: a static analysis and synthesis approach

CHEN, 2024

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Document ID
11601689083180420194
Author
CHEN K
Publication year

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Snippet

Questa tesi presenta una metodologia e un'estensione della toolchain per la sintesi del parallelismo basato su task di OpenMP su acceleratori FPGA. Sebbene il modello parallelo for di OpenMP sia stato mappato con successo sull'hardware tramite tecniche di High-Level …
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Classifications

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    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformations of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/456—Parallelism detection
    • G—PHYSICS
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    • G06F8/44—Encoding
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    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
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    • G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
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