Preiss et al., 2009 - Google Patents
Advanced clockgating schemes for fused-multiply-add-type floating-point unitsPreiss et al., 2009
View PDF- Document ID
- 12002409084096265461
- Author
- Preiss J
- Boersma M
- Mueller S
- Publication year
- Publication venue
- 2009 19th IEEE Symposium on Computer Arithmetic
External Links
Snippet
The paper introduces fine-grain clockgating schemes for fused multiply-add-type floating- point units (FPU). The clockgating is based on instruction type, precision and operand values. The presented schemes focus on reducing the power at peak performance, where …
- 230000001603 reducing 0 abstract description 11
Classifications
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- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
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- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
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- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
- G06F1/3237—Power saving by disabling clock generation or distribution
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- G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system, floating-point numbers
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- G—PHYSICS
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