[go: up one dir, main page]

Peterson et al., 2019 - Google Patents

Power-Gating Models for Rapid Design Exploration

Peterson et al., 2019

Document ID
12114382013964261995
Author
Peterson D
Bringmann O
Publication year
Publication venue
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)

External Links

Snippet

Power gating (PG) is an effective method to reduce leakage currents in an SoC design during run-time. It dynamically shuts down components using a network of sleep transistors but requires a detailed analysis to scale this network appropriately with respect to area wake …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G06F17/5031—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/504—Formal methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/84—Timing analysis and optimization
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. varying supply voltage
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components

Similar Documents

Publication Publication Date Title
Sirichotiyakul et al. Duet: An accurate leakage estimation and optimization tool for dual-V/sub t/circuits
Alioto et al. Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part I—Methodology and design strategies
Yeap Practical low power digital VLSI design
Nithin et al. Dynamic voltage (IR) drop analysis and design closure: Issues and challenges
Moreira et al. Impact of C-elements in asynchronous circuits
Chadha et al. An ASIC low power primer: analysis, techniques and specification
US7240304B2 (en) Method for voltage drop analysis in integreted circuits
Boliolo et al. Gate-level power and current simulation of CMOS integrated circuits
Verma et al. More precise FPGA power estimation and validation tool (FPEV_Tool) for low power applications
Lasbouygues et al. Logical effort model extension to propagation delay representation
Kashyap et al. A nonlinear cell macromodel for digital applications
Srivastava et al. Interdependent latch setup/hold time characterization via Euler-Newton curve tracing on state-transition equations
Dhanwada et al. Leakage power contributor modeling
Sharma et al. Effective drive current for near-threshold CMOS circuits’ performance evaluation: Modeling to circuit design techniques
Peterson et al. Power-Gating Models for Rapid Design Exploration
Calimera et al. Temperature-Insensitive Dual-$ V_ {\rm th} $ Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence
Monteiro et al. Power analysis and optimization from circuit to register-transfer levels
Li et al. Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis
Hoyer et al. Modelling the impact of high level leakage optimization techniques on the delay of RT-components
Haataja Register-transfer level power estimation and reduction methodologies of digital system-on-chip building blocks
Moreira et al. Electrical characterization of a C-Element with LiChEn
Agrawal et al. A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs
US8099704B1 (en) Performance improvements in an integrated circuit by selectively applying forward bias voltages
Λιλίτσης Power analysis engine implementation for VLSI digital systems
Rjoub et al. Graph modeling for Static Timing Analysis at transistor level in nano-scale CMOS circuits