Skoufis, 2009 - Google Patents
Coping with delays and hazards in buses and random logic in deep sub-micronSkoufis, 2009
- Document ID
- 12412944047268241765
- Author
- Skoufis M
- Publication year
External Links
Snippet
A new data capturing technique for a potentially coupled bus of lines is proposed that always accommodates fast operation. The proposed method utilizes multiple reference voltages available within a line's receiving logic and the initial conditions of the involved …
- 230000001934 delay 0 title description 8
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/0033—Radiation hardening
- H03K19/00338—In field effect transistor circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/007—Fail-safe circuits
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8566770B2 (en) | Layout method for soft-error hard electronics, and radiation hardened logic cell | |
| US8191021B2 (en) | Single event transient mitigation and measurement in integrated circuits | |
| Li et al. | Double node upsets hardened latch circuits | |
| US8468484B2 (en) | Layout method for soft-error hard electronics, and radiation hardened logic cell | |
| US20160048624A1 (en) | Circuit and layout design methods and logic cells for soft error hard integrated circuits | |
| Sayil | Soft error mechanisms, modeling and mitigation | |
| Sayil | A survey of circuit-level soft error mitigation methodologies | |
| Maharrey et al. | Dual-interlocked logic for single-event transient mitigation | |
| Kannaujiya et al. | Radiation effects in vlsi circuits-part ii: Hardening techniques | |
| US10181851B2 (en) | Dual interlocked logic circuits | |
| Paparsenos et al. | Radiation-hardened latch design with triple-node-upset recoverability | |
| Skoufis | Coping with delays and hazards in buses and random logic in deep sub-micron | |
| CN101069351A (en) | Electronic device having logic circuitry and method for designing logic circuitry | |
| Chen et al. | Improving circuit robustness with cost-effective soft-error-tolerant sequential elements | |
| Thorp et al. | Analysis of blocking dynamic circuits | |
| Yazdanshenas et al. | A scalable dependability scheme for routing fabric of SRAM-based reconfigurable devices | |
| El-Maleh et al. | Time redundancy and gate sizing soft error-tolerant based adder design | |
| Shao et al. | Separate dual-transistor registers: a circuit solution for on-line testing of transient error in UDMC-IC | |
| Sayil | Single Event Soft Errors | |
| Maharrey | Dual interlocked logic: A radiation-hardened-by-design technique for single-event logic errors | |
| Skoufis et al. | An Online Failure Detection Method for Data Buses Using Multithreshold Receiving Logic | |
| Oliveira | Analysis of radiation effects in full adder circuits at 7nm FinFET technology | |
| Sayil | Soft Error Mechanisms, Modeling and Mitigation | |
| Barbirotta et al. | Fault tolerant voting circuits: A Dual-Modular-Redundancy approach for Single-Event-Transient mitigation | |
| Lamichhane | Transmission Gate Based Soft Error Mitigation Technique for NCL Threshold Gate |