Wang et al., 2024 - Google Patents
Don't Repeat Yourself! Coarse-Grained Circuit Deduplication to Accelerate RTL SimulationWang et al., 2024
View PDF- Document ID
- 13460303230228169269
- Author
- Wang H
- Nijssen T
- Beamer S
- Publication year
- Publication venue
- Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 4
External Links
Snippet
Designing a digital integrated circuit requires many register transfer level (RTL) simulations for design, debugging, and especially verification. To cope with the slow speed of RTL simulation, industry frequently uses private server farms to run many simulations in parallel …
- 238000004088 simulation 0 title abstract description 126
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/44—Arrangements for executing specific programmes
- G06F9/455—Emulation; Software simulation, i.e. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformations of program code
- G06F8/41—Compilation
- G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
- G06F8/456—Parallelism detection
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformations of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/70—Software maintenance or management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3457—Performance evaluation by simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/68—Processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Ubal et al. | Multi2Sim: A simulation framework for CPU-GPU computing | |
| Bortolotti et al. | Virtualsoc: A full-system simulation environment for massively parallel heterogeneous system-on-chip | |
| Kraus et al. | Accelerating a C++ CFD code with OpenACC | |
| Wang et al. | Repcut: Superlinear parallel rtl simulation with replication-aided partitioning | |
| TW202507503A (en) | System for design and manufacturing of integrated circuitry (ic) | |
| Guo et al. | Tapa: A scalable task-parallel dataflow programming framework for modern fpgas with co-optimization of hls and physical design | |
| Matthews et al. | MosaicSim: A lightweight, modular simulator for heterogeneous systems | |
| Wang et al. | Don't Repeat Yourself! Coarse-Grained Circuit Deduplication to Accelerate RTL Simulation | |
| Giorgi et al. | A design space exploration tool set for future 1k-core high-performance computers | |
| Riedel et al. | Banshee: A fast LLVM-based RISC-V binary translator | |
| Sorensen et al. | A simulator and compiler framework for agile hardware-software co-design evaluation and exploration | |
| Banerjee et al. | A highly configurable hardware/Software stack for DNN inference acceleration | |
| Janik et al. | An overview of altera sdk for opencl: A user perspective | |
| Voss et al. | On predictable reconfigurable system design | |
| Raghav et al. | Full system simulation of many-core heterogeneous SoCs using GPU and QEMU semihosting | |
| Nanjundappa et al. | Accelerating systemc simulations using gpus | |
| Giorgi et al. | Translating timing into an architecture: the synergy of COTSon and HLS (domain expertise—designing a computer architecture via HLS) | |
| Bombieri et al. | HDTLib: an efficient implementation of SystemC data types for fast simulation at different abstraction levels | |
| Wan et al. | HeteroPP: A directive‐based heterogeneous cooperative parallel programming framework | |
| Bortolotti et al. | VirtualSoC: A research tool for modern MPSoCs | |
| Rekik et al. | Virtual prototyping of multiprocessor architectures using the open virtual platform | |
| Brandner et al. | DSP instruction set simulation | |
| Lonardi et al. | On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms | |
| Stitt et al. | Thread warping: Dynamic and transparent synthesis of thread accelerators | |
| Schirrmeister | Improving Emulation Throughput for Multi-Project SoC Designs |