[go: up one dir, main page]

Caruso, 2020 - Google Patents

Izhikevich neural model and STDP learning algorithm mapping on spiking neural network hardware emulator

Caruso, 2020

View PDF
Document ID
14019499371161222766
Author
Caruso A
Publication year

External Links

Continue reading at webthesis.biblio.polito.it (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computer systems based on biological models
    • G06N3/02Computer systems based on biological models using neural network models
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/0635Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means using analogue means
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computer systems based on biological models
    • G06N3/02Computer systems based on biological models using neural network models
    • G06N3/04Architectures, e.g. interconnection topology
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computer systems based on biological models
    • G06N3/02Computer systems based on biological models using neural network models
    • G06N3/08Learning methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computer systems based on biological models
    • G06N3/02Computer systems based on biological models using neural network models
    • G06N3/10Simulation on general purpose computers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • G06F17/11Complex mathematical operations for solving equations, e.g. nonlinear equations, general mathematical optimization problems
    • G06F17/13Differential equations
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00Computer systems utilising knowledge based models
    • G06N5/04Inference methods or devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00Computer systems utilising knowledge based models
    • G06N5/02Knowledge representation
    • G06N5/022Knowledge engineering, knowledge acquisition
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N99/00Subject matter not provided for in other groups of this subclass
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3457Performance evaluation by simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/68Processors

Similar Documents

Publication Publication Date Title
Cheung et al. NeuroFlow: a general purpose spiking neural network simulation platform using customizable processors
Goodman et al. Brian: a simulator for spiking neural networks in python
Pearson et al. Implementing spiking neural networks for real-time signal-processing and control applications: A model-validated FPGA approach
Blundell et al. Code generation in computational neuroscience: a review of tools and techniques
Witbrock et al. An implementation of backpropagation learning on GF11, a large SIMD parallel computer
Smaragdos et al. FPGA-based biophysically-meaningful modeling of olivocerebellar neurons
Savich et al. A scalable pipelined architecture for real-time computation of MLP-BP neural networks
Sanaullah et al. SNNs model analyzing and visualizing experimentation using RAVSim
Ward et al. Beyond LIF neurons on neuromorphic hardware
Uludağ et al. Bio-realistic neural network implementation on loihi 2 with izhikevich neurons
Caruso Izhikevich neural model and STDP learning algorithm mapping on spiking neural network hardware emulator
Czibula et al. An effective approach for determining the class integration test order using reinforcement learning
Linssen et al. NESTML: a generic modeling language and code generation tool for the simulation of spiking neural networks with advanced plasticity rules
Bautembach et al. Faster and simpler SNN simulation with work queues
Jin Parallel simulation of neural networks on spinnaker universal neuromorphic hardware
Yi et al. Implementation of hodgkin-huxley spiking neuron model using fpga
López-Asunción et al. Flexible Deep-pipelined FPGA-based Accelerator for Spiking Neural Networks
Drewes et al. Brainlab: a python toolkit to aid in the design, simulation, and analysis of spiking neural networks with the neocortical simulator
Huang et al. Teaching hardware implementation of neural networks using high-level synthesis in less than four hours for engineering education of intelligent embedded computing
Sura et al. Using Structured Input and Modularity for Improved Learning
Beeman Introduction to realistic neural modeling
WO2025017094A1 (en) Method to build and deploy spiking neural networks on hardware device
Isaksen DESIGN AND TEST OF A NEURAL MICROPROCESSOR
Rivera et al. A High-Level Interface for Accelerating Spiking Neural Networks on the Edge with Heterogeneous Hardware: Enabling Rapid Prototyping of Training Algorithms and Topologies on Field-Programmable Gate Arrays
JP3921259B2 (en) Non-symbol processing device that enables symbolic processing, information processing system, and automatic coder thereof