Wu et al., 2018 - Google Patents
A digital background calibration scheme for pipelined ADCs using multiple-correlation estimationWu et al., 2018
- Document ID
- 14815752971681236698
- Author
- Wu M
- Hong H
- Publication year
- Publication venue
- 2018 IEEE International Symposium on Circuits and Systems (ISCAS)
External Links
Snippet
This paper proposes a digital background calibration scheme for calibrating the linear and the third-order nonlinear gain errors of the residue amplifiers (RAs) in pipelined ADCs. It is based on a novel multiple-correlation estimation (MCE) technique. We define two correction …
- 229920002574 CR-39 0 title abstract description 61
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- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
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- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
- H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
- H03M1/0682—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
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- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
- H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
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- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain by continuously permuting the elements used, i.e. dynamic element matching
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