[go: up one dir, main page]

Zhao et al., 2006 - Google Patents

Mechanical modeling and analysis of board level drop test of electronic package

Zhao et al., 2006

Document ID
1536806652717911712
Author
Zhao J
Garner L
Publication year
Publication venue
56th Electronic Components and Technology Conference 2006

External Links

Snippet

Solder joint reliability (SJR) issues caused by drop impact have received more and more attention from the industry in recent years. To assess the SJR in drop shock, electronic packages are generally surface mounted on a printed circuit board (PCB) whose oscillations …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING STRUCTURES OR APPARATUS NOT OTHERWISE PROVIDED FOR
    • G01M7/00—Vibration-testing of structures; Shock-testing of structures
    • G01M7/08—Shock-testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N2203/00—Investigating strength properties of solid materials by application of mechanical stress
    • G01N2203/02—Details not specific for a particular testing method

Similar Documents

Publication Publication Date Title
Tee et al. Novel numerical and experimental analysis of dynamic responses under board level drop test
Luan et al. Advanced numerical and experimental techniques for analysis of dynamic responses and solder joint reliability during drop impact
Tee et al. Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact
Luan et al. Modal analysis and dynamic responses of board level drop test
Lall et al. Design envelopes and optical feature extraction techniques for survivability of SnAg leadfree packaging architectures under shock and vibration
Zhao et al. Mechanical modeling and analysis of board level drop test of electronic package
Luan et al. Dynamic responses and solder joint reliability under board level drop test
Syed et al. A methodology for drop performance modeling and application for design optimization of chip-scale packages
Chaparala et al. Effect of geometry and temperature cycle on the reliability of WLCSP solder joints
Lall et al. Modeling and reliability characterization of area-array electronics subjected to high-g mechanical shock up to 50,000 g
Thukral et al. Understanding the impact of PCB changes in the latest published JEDEC board level drop test method
Chandana et al. Drop test analysis of ball grid array package using finite element methods
Sinha et al. Predictive Solder Joint Reliability Modeling for Early Risk Assessment
Agrawal et al. Board level energy correlation and interconnect reliability modeling under drop impact
Gu et al. Drop test simulation and DOE analysis for design optimization of microelectronics packages
Al-Yafawi et al. Random vibration test for electronic assemblies fatigue life estimation
Yeh et al. Ultra-thin package board level drop impact modeling and validation
Ranouta et al. Shock performance study of solder joints in wafer level packages
Ahmed et al. Effects of heatsink application and PCB design variations on BGA solder joint reliability
Loh et al. Solder joint reliability prediction of flip chip packages under shock loading environment
Pitarresi et al. A parametric solder joint reliability model for wafer level-chip scale package
Zhao et al. Improvement of JEDEC drop test in SJR qualification through alternative test board design
Dhiman Study on finite element modeling of dynamic behaviors for wafer level packages under impact loading
Bentata et al. Study of JEDEC B-condition JESD22-B111 standard for drop test reliability of Chip Scale Packages
Kramer et al. Lifetime modeling for jedec drop tests