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Lee et al., 2013 - Google Patents

Eco cost measurement and incremental gate sizing for late process changes

Lee et al., 2013

View PDF
Document ID
1540860571258577227
Author
Lee J
Gupta P
Publication year
Publication venue
ACM Transactions on Design Automation of Electronic Systems (TODAES)

External Links

Snippet

Changes in the manufacturing process parameters may create timing violations in a design, making it necessary to perform an engineering change order (ECO) to correct these problems. We present a framework for performing incremental gate sizing for process …
Continue reading at nanocad.ee.ucla.edu (PDF) (other versions)

Classifications

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    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
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    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
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