[go: up one dir, main page]

Attaoui et al., 2021 - Google Patents

A new MBFF merging strategy for post-placement power optimization of IoT devices

Attaoui et al., 2021

Document ID
15551648468055239811
Author
Attaoui Y
Chentouf M
Ismaili Z
El Mourabit A
Publication year
Publication venue
2021 IEEE/ACS 18th International Conference on Computer Systems and Applications (AICCSA)

External Links

Snippet

Recently power has become the most important factor in VLSI design. As clock network is the largest design element in terms of power consumption in modern low-power Very Large Scale Integration (VLSI) Designs and IoT applications, several studies have been made in …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072—Floorplanning, e.g. partitioning, placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/504—Formal methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30286—Information retrieval; Database structures therefor; File system structures therefor in structured data stores
    • G06F17/30386—Retrieval requests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12—Design for manufacturability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application

Similar Documents

Publication Publication Date Title
Kahng et al. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
US9852253B2 (en) Automated layout for integrated circuits with nonstandard cells
Kuon et al. Measuring the gap between FPGAs and ASICs
Pedram Power minimization in IC design: Principles and applications
US5696694A (en) Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist
US8434047B1 (en) Multi-level clock gating circuitry transformation
Chowdhary et al. Extraction of functional regularity in datapath circuits
Amarú et al. Logic optimization and synthesis: Trends and directions in industry
Vishnu et al. Clock tree synthesis techniques for optimal power and timing convergence in soc partitions
US7092838B1 (en) Method and apparatus for the analysis and optimization of variability in nanometer technologies
Attaoui et al. Clock gating efficiency and impact on power optimization during synthesis flow
US8069424B2 (en) Generating a base curve database to reduce storage cost
Attaoui et al. A new MBFF merging strategy for post-placement power optimization of IoT devices
US6834379B2 (en) Timing path detailer
Hsu et al. Crosstalk-aware power optimization with multi-bit flip-flops
Hsu et al. Crosstalk-aware multi-bit flip-flop generation for power optimization
US10474778B2 (en) Systems and methods for top level integrated circuit design
Kalargaris et al. STA compatible backend design flow for TSV-based 3-D ICs
Chentouf et al. Power-aware hold optimization for ASIC physical synthesis
Pasricha et al. Capps: A framework for power–performance tradeoffs in bus-matrix-based on-chip communication architecture synthesis
Monteiro et al. FSM decomposition by direct circuit manipulation applied to low power design
Huang et al. State re-encoding for peak current minimization
KR102656245B1 (en) Method for providing complex logic cell for adjusting output phase and computing system for generating the same
Torrubia Ollero Efficient implementation of a Content-Addressable Memory in a 22nm technology
Nguyen et al. A Low-Power ASIC Implementation of Multi-Core OpenSPARC T1 Processor on 90nm CMOS Process