Sharma et al., 2021 - Google Patents
Real-time automated register abstraction active power-aware electronic system level verification frameworkSharma et al., 2021
- Document ID
- 15500724841758547760
- Author
- Sharma G
- Bhargava L
- Kumar V
- Publication year
- Publication venue
- Integration
External Links
Snippet
All modern low power system on a chip (SoC) architectures are equipped with an in-built power management system. Every new system is expected to have more features and lower power consumption, resulting in a continuous demand to improve energy efficiency. To cope …
- 238000004088 simulation 0 abstract description 78
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
- G06F17/5031—Timing analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
- G06F1/3237—Power saving by disabling clock generation or distribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/68—Processors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/86—Hardware-Software co-design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Keating et al. | Reuse methodology manual for system-on-a-chip designs | |
| Keating et al. | Low power methodology manual: for system-on-chip design | |
| US7725848B2 (en) | Predictable design of low power systems by pre-implementation estimation and optimization | |
| US8176453B2 (en) | Power-aware debugging | |
| Dhanwada et al. | A power estimation methodology for systemc transaction level models | |
| US20130179142A1 (en) | Distributed parallel simulation method and recording medium for storing the method | |
| US6513145B1 (en) | Method for estimating the power consumed in a microprocessor | |
| Bouhadiba et al. | System-level modeling of energy in TLM for early validation of power and thermal management | |
| US11231769B2 (en) | Sequencer-based protocol adapter | |
| Bergamaschi et al. | State-based power analysis for systems-on-chip | |
| EP3593225A1 (en) | An operating point controller for circuit regions in an integrated circuit | |
| Bricaud | Reuse methodology manual for system-on-a-chip designs | |
| Hazra et al. | Formal verification of architectural power intent | |
| Mbarek et al. | A methodology for power-aware transaction-level models of systems-on-chip using UPF standard concepts | |
| Mischkalla et al. | Advanced SoC virtual prototyping for system-level power planning and validation | |
| Nebel | High-level power estimation and analysis | |
| Macko et al. | Power-management high-level synthesis | |
| Hazra et al. | POWER-TRUCTOR: An integrated tool flow for formal verification and coverage of architectural power intent | |
| Pham et al. | Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor | |
| Sharma et al. | Real-time automated register abstraction active power-aware electronic system level verification framework | |
| Mukheijee et al. | Clock and power gating with timing closure | |
| Mischkalla et al. | Architectural low-power design using transaction-based system modeling and simulation | |
| Ahuja | High level power estimation and reduction techniques for power aware hardware design | |
| US7503025B2 (en) | Method to generate circuit energy models for macros containing internal clock gating | |
| Harinarayan et al. | Automated Full Chip SPICE simulations with self-checking assertions for last mile verification & first pass Silicon of mixed signal SoCs |