[go: up one dir, main page]

Huang et al., 2025 - Google Patents

MOMC3D: A Novel Multi-Objective Optimization Method With Mixed-Coding Strategy for Standard Cells in Chip 3D Placement

Huang et al., 2025

Document ID
15664740646535723954
Author
Huang H
Zhao H
Liu J
Publication year
Publication venue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

External Links

Snippet

The integrated circuit for 3D chip placement has attracted much attention in recent years, but its complex netlist structure poses significant challenges in optimizing 3D chip placement. However, the current algorithms for 3D chip placement have not considered further …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072—Floorplanning, e.g. partitioning, placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30286—Information retrieval; Database structures therefor; File system structures therefor in structured data stores
    • G06F17/30386—Retrieval requests
    • G06F17/30424—Query processing
    • G06F17/30533—Other types of queries
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/08—Multi-objective optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computer systems based on biological models
    • G06N3/12—Computer systems based on biological models using genetic models
    • G06N3/126—Genetic algorithms, i.e. information processing using digital simulations of the genetic system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F19/00—Digital computing or data processing equipment or methods, specially adapted for specific applications
    • G06F19/10—Bioinformatics, i.e. methods or systems for genetic or protein-related data processing in computational molecular biology
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12—Design for manufacturability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computer systems based on biological models
    • G06N3/02—Computer systems based on biological models using neural network models
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N99/00—Subject matter not provided for in other groups of this subclass

Similar Documents

Publication Publication Date Title
Cheng et al. On joint learning for solving placement and routing in chip design
Sarrafzadeh et al. Modern placement techniques
Lu et al. The law of attraction: Affinity-aware placement optimization using graph neural networks
Xiao et al. Practical placement and routing techniques for analog circuit designs
Lin et al. Asynchronous reinforcement learning framework and knowledge transfer for net-order exploration in detailed routing
Liu et al. MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs
US7003749B2 (en) Constraint data management for electronic design automation
CN118661174A (en) Automated transistor-level placement for integrated circuit design
Xu et al. Memristive crossbar mapping for neuromorphic computing systems on 3D IC
Zou et al. Incremental 3-D global routing considering cell movement and complex routing constraints
Cuesta et al. 3D thermal-aware floorplanner using a MILP approximation
Le et al. Toward reinforcement learning-based rectilinear macro placement under human constraints
Huang et al. Routability-driven power/ground network optimization based on machine learning
Huang et al. MOMC3D: A Novel Multi-Objective Optimization Method With Mixed-Coding Strategy for Standard Cells in Chip 3D Placement
Ying et al. An analytical approach to floorplanning for hierarchical building blocks layout (VLSI)
Liu et al. Performance-driven X-architecture routing algorithm for artificial intelligence chip design in smart manufacturing
Knechtel et al. Multi-objective 3D floorplanning with integrated voltage assignment
Maji et al. Multi-Objective Optimization for Common-Centroid Placement of Analog Transistors
Wang et al. AIPlace: Analog IC Placement with Multi-Task Learning Framework
Zhu et al. High-performance placement engine for modern large-scale fpgas with heterogeneity and clock constraints
Jiang et al. CU. POKer: Placing DNNs on WSE With Optimal Kernel Sizing and Efficient Protocol Optimization
Du et al. JigsawPlanner: Jigsaw-like Floorplanner for Eliminating Whitespace and Overlap among Complex Rectilinear Modules
Evans et al. VLSI-Inspired Design Automation for Scalable Power Electronics Layout Optimization
CN116245066B (en) Chip division placement simulation method and device in 3D scene and computer equipment
Lee et al. MB $^{\ast} $-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design