[go: up one dir, main page]

Kalb et al., 2016 - Google Patents

Enabling dynamic and partial reconfiguration in Xilinx SDSoC

Kalb et al., 2016

Document ID
15668967015160266497
Author
Kalb T
Göhringer D
Publication year
Publication venue
2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

External Links

Snippet

In the past years dynamic partial reconfiguration (DPR) has been established as a well- known technique for systems featuring a field programmable gate array (FPGA). Systems-on- Chip (SoC) with an ARM processor ease the utilization of DPR and motivate its …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/44Arrangements for executing specific programmes
    • G06F9/455Emulation; Software simulation, i.e. virtualisation or emulation of application or operating system execution engines
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformations of program code
    • G06F8/41Compilation
    • G06F8/44Encoding
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/30Creation or generation of source code
    • G06F8/34Graphical or visual programming
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/30Creation or generation of source code
    • G06F8/36Software reuse
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/362Software debugging
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/78Architectures of general purpose stored programme computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored programme computers comprising a single central processing unit with reconfigurable architecture
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/70Software maintenance or management
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/60Software deployment
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/68Processors
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application

Similar Documents

Publication Publication Date Title
US7503027B1 (en) Hardware description language code generation from a state diagram
Koch et al. FPGAs for software programmers
Chou et al. The chinook hardware/software co-synthesis system
KR100775547B1 (en) Automatic Processor Generation System and Method for Designing Configurable Processors
EP0853792B1 (en) Method of producing a digital signal processor
KR20220002644A (en) Creation of Dynamic Design Flows for Integrated Circuits
Koul et al. AHA: An agile approach to the design of coarse-grained reconfigurable accelerators and compilers
WO2011156234A1 (en) Systems and methods for circuit design, synthesis, simulation, and modeling
D'Andrea et al. Self-adaptive loop for CPSs: is the dynamic partial reconfiguration profitable?
Kalb et al. Enabling dynamic and partial reconfiguration in Xilinx SDSoC
Xiao et al. HiPR: High-level partial reconfiguration for fast incremental FPGA compilation
Wang et al. Automated field-programmable compute accelerator design using partial evaluation
Wilson et al. Seiba: An FPGA overlay-based approach to rapid application development
Kang et al. A design and test technique for embedded software
Ibellaatti et al. HERMES: qualification of High pErformance pRogrammable Microprocessor and dEvelopment of Software ecosystem
Zulberti et al. A script-based cycle-true verification framework to speed-up hardware and software co-design of system-on-chip exploiting RISC-V architecture
Fricke et al. Automatic tool-flow for mapping applications to an application-specific cgra architecture
Todman et al. Verification of streaming hardware and software codesigns
Quadri MARTE based model driven design methodology for targeting dynamically reconfigurable FPGA based SoCs
Groza et al. A self-reconfigurable platform for built-in self-test applications
US20100115255A1 (en) System and Method of Dynamically Building a Behavior Model on a Hardware System
Guillet et al. Modeling and formal control of partial dynamic reconfiguration
Picard et al. Multilevel simulation of heterogeneous reconfigurable platforms
Robles Pre-silicon and post-silicon testing of SIWA, a low-power RISC-V microcontroller.
Zakiy Hw-sw co-design of an on-chip ijtag dependability processor