[go: up one dir, main page]

Liu et al., 2019 - Google Patents

LPM: A systematic methodology for concurrent data access pattern optimization from a matching perspective

Liu et al., 2019

Document ID
15945093856777366447
Author
Liu Y
Sun X
Publication year
Publication venue
IEEE Transactions on Parallel and Distributed Systems

External Links

Snippet

As applications become increasingly data intensive, conventional computing systems become increasingly inefficient due to data access performance bottlenecks. While intensive efforts have been made in developing new memory technologies and in designing special …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3442—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment for planning or managing the needed capacity
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/885—Monitoring specific for caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/86—Event-based monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity

Similar Documents

Publication Publication Date Title
Wang et al. GPGPU performance estimation with core and memory frequency scaling
Brais et al. A survey of cache simulators
Hager et al. Exploring performance and power properties of modern multi‐core chips via simple machine models
Molka et al. Detecting memory-boundedness with hardware performance counters
Diamond et al. Evaluation and optimization of multicore performance bottlenecks in supercomputing applications
Wang et al. Mdm: The gpu memory divergence model
Chen et al. Modeling cache contention and throughput of multiprogrammed manycore processors
Chen et al. Performance and power modeling in a multi-programmed multi-core environment
Tudor et al. A practical approach for performance analysis of shared-memory programs
Pieper et al. High level cache simulation for heterogeneous multiprocessors
Liu et al. LPM: A systematic methodology for concurrent data access pattern optimization from a matching perspective
Jahre et al. GDP: Using dataflow properties to accurately estimate interference-free performance at runtime
Liu et al. LPM: concurrency-driven layered performance matching
Liu et al. Hardware support for accurate per-task energy metering in multicore systems
Liu et al. A study on modeling and optimization of memory systems
Noorshams et al. Modeling of i/o performance interference in virtualized environments with queueing petri nets
John 8.2 performance evaluation: Techniques, tools, and benchmarks
Yang et al. HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs
Casas et al. Evaluation of HPC applications’ memory resource consumption via active measurement
Duan et al. Predicting architectural vulnerability on multithreaded processors under resource contention and sharing
Sharapov et al. A case study in top-down performance estimation for a large-scale parallel application
Velásquez et al. BADCO: Behavioral Application-Dependent Superscalar Core Models
Liu et al. CaL: Extending data locality to consider concurrency for performance optimization
Liang et al. Quantifying Resource Contention of Co-located Workloads with the System-level Entropy
Jaleel et al. Cmp $ im: A binary instrumentation approach to modeling memory behavior of workloads on cmps