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Gort et al., 2011 - Google Patents

Accelerating FPGA routing through parallelization and engineering enhancements special section on PAR-CAD 2010

Gort et al., 2011

Document ID
16283365057781230385
Author
Gort M
Anderson J
Publication year
Publication venue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

External Links

Snippet

We present parallelization and heuristic techniques to reduce the run-time of field- programmable gate array (FPGA) negotiated congestion routing. Two heuristic optimizations provide over 3× speedup versus a sequential baseline. In our parallel approach, sets of …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
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    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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    • G06F9/46—Multiprogramming arrangements
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