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Trevillyan et al., 2004 - Google Patents

An integrated environment for technology closure of deep-submicron IC designs

Trevillyan et al., 2004

Document ID
16486690330553844532
Author
Trevillyan L
Kung D
Puri R
Reddy L
Kazda M
Publication year
Publication venue
IEEE Design & Test of Computers

External Links

Snippet

With larger chip images and increasingly aggressive technologies, key design processes must interoperate, PDS, a physical-synthesis system, accomplishes technology closure through interacting processes of logic optimization, placement, timing, clock insertion, and …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G06F17/5031—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072—Floorplanning, e.g. partitioning, placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
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    • G06F17/5077—Routing
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    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
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    • G06F17/50—Computer-aided design
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    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning

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