[go: up one dir, main page]

Venkatesan et al., 2015 - Google Patents

Cache design with domain wall memory

Venkatesan et al., 2015

Document ID
1732827684747343880
Author
Venkatesan R
Kozhikkottu V
Sharad M
Augustine C
Raychowdhury A
Roy K
Raghunathan A
Publication year
Publication venue
IEEE Transactions on Computers

External Links

Snippet

Domain wall memory (DWM) is a recently developed spin-based memory technology in which several bits of data are densely packed into the domains of a ferromagnetic wire. DWM has shown great promise in enabling non-volatile memory with very high density and …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores
    • G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using magnetic elements
    • G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using magnetic elements using thin films in plane structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell

Similar Documents

Publication Publication Date Title
Venkatesan et al. Cache design with domain wall memory
Aly et al. The N3XT approach to energy-efficient abundant-data computing
Park et al. Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture
Wu et al. Hybrid cache architecture with disparate memory technologies
Ranjan et al. Approximate storage for energy efficient spintronic memories
Venkatesan et al. Stag: Spintronic-tape architecture for gpgpu cache hierarchies
Mittal et al. A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches
Venkatesan et al. Dwm-tapestri-an energy efficient all-spin cache using domain wall shift based writes
Li et al. Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective
Wu et al. Power and performance of read-write aware hybrid caches with non-volatile memories
Wang et al. An energy-efficient nonvolatile in-memory computing architecture for extreme learning machine by domain-wall nanowire devices
Kwon et al. AWARE (asymmetric write architecture with redundant blocks): A high write speed STT-MRAM cache architecture
Senni et al. Exploring MRAM technologies for energy efficient systems-on-chip
Sun et al. Array organization and data management exploration in racetrack memory
Inci et al. DeepNVM++: Cross-layer modeling and optimization framework of nonvolatile memories for deep learning
Patel et al. Reducing switching latency and energy in STT-MRAM caches with field-assisted writing
Motaman et al. Synergistic circuit and system design for energy-efficient and robust domain wall caches
Wang et al. An ultralow-power memory-based big-data computing platform by nonvolatile domain-wall nanowire devices
Xue et al. An adaptive 3T-3MTJ memory cell design for STT-MRAM-based LLCs
Ranjan et al. DyReCTape: A dynamically reconfigurable cache using domain wall memory tapes
Chen et al. Process variation aware data management for magnetic skyrmions racetrack memory
Paul et al. Energy-efficient reconfigurable computing using a circuit-architecture-software co-design approach
Bi et al. Cross-layer optimization for multilevel cell STT-RAM caches
Bi et al. Analysis and optimization of thermal effect on STT-RAM Based 3-D stacked cache design
Chatterjee et al. A scalable design methodology for energy minimization of STTRAM: A circuit and architecture perspective