[go: up one dir, main page]

Low, 2003 - Google Patents

Using the RGMII to Interface with the Gigabit Ethernet MAC

Low, 2003

View PDF
Document ID
1758247784371963939
Author
Low M
Publication year

External Links

Snippet

Implementation The RGMII adaptation module is connected to the RX data, RX error, and RX data valid ports on the receive side of the 1-Gigabit Ethernet MAC core, and to the TX data, TX error, and TX enable ports on the transmit side. All signals are synchronous with a …
Continue reading at application-notes.digchip.com (PDF) (other versions)

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
    • H04L12/46—Interconnection of networks
    • H04L12/4604—LAN interconnection over a backbone network, e.g. Internet, Frame Relay
    • H04L12/462—LAN interconnection over a bridge based backbone
    • H04L12/4625—Single bridge functionality, e.g. connection of two networks over a single bridge
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/26—Monitoring arrangements; Testing arrangements
    • H04L12/2697—Testing equipment; Routine testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Application specific switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Application independent communication protocol aspects or techniques in packet data networks
    • H04L69/08—Protocols for interworking or protocol conversion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Application independent communication protocol aspects or techniques in packet data networks
    • H04L69/18—Multi-protocol handler, e.g. single device capable of handling multiple protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Application independent communication protocol aspects or techniques in packet data networks
    • H04L69/12—Protocol engines, e.g. VLSIs or transputers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing packet switching networks
    • H04L43/50—Testing arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L29/00—Arrangements, apparatus, circuits or systems, not covered by a single one of groups H04L1/00 - H04L27/00 contains provisionally no documents
    • H04L29/02—Communication control; Communication processing contains provisionally no documents
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic regulation in packet switching networks
    • H04L47/10—Flow control or congestion control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Similar Documents

Publication Publication Date Title
US6044087A (en) Interface for a highly integrated ethernet network element
US7843216B2 (en) Techniques for optimizing design of a hard intellectual property block for data transmission
US7426599B2 (en) Systems and methods for writing data with a FIFO interface
US6625675B2 (en) Processor for determining physical lane skew order
US7782888B2 (en) Configurable ports for a host ethernet adapter
US8094668B1 (en) Physical layer device including a serial media independent interface (SMII)
US8990457B2 (en) Serial communication device with MAC, a mask circuit, and buffer that conforms to serial media independent interface (SMII) in order to reduce power consumption
US6934866B2 (en) Network interface using programmable delay and frequency doubler
Födisch et al. A synchronous Gigabit Ethernet protocol stack for high-throughput UDP/IP applications
US6023476A (en) Signal delays in a logical repeater set
Low Using the RGMII to Interface with the Gigabit Ethernet MAC
EP1158735A1 (en) TDMA bus interface, system for communicating data, and method
Kerling Design, implementation, and test of a tri-mode Ethernet MAC on an FPGA
Nurmi et al. Prototyping 40g ethernet communication on fpga
Latif et al. Field-programmable gate array implementation on ethernet MAC for high speed secure data communication
IHAMÄKI FPGA BASED ETHERNET MEDIA LEVEL TESTER
Zhang et al. Design of a high speed XAUI based on dynamic reconfigurable transceiver IP core
Wang et al. Design and Realization of Gigabit Ethernet Interface Based on FPGA
Kundoor Design and implementation of a 10 Gigabit Ethernet XAUI test systems
Natchinarkiniyan et al. SpaceWire to SpaceFibre bridge
US7861018B2 (en) System for transmitting data between transmitter and receiver modules on a channel provided with a flow control link
Wu et al. The MAC layer packet transceiver system based on FPGA design and implementation
Henriksson In-Line CRC Calculation and Scheduling for 10 Gigabit Ethernet Transmission
Duman UNIBUS: A universal hardware architecture for serial bus interfaces with real-time support
Kim et al. Common hardware-in-the-loop framework development