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Lo et al., 2007 - Google Patents

STEAC: A platform for automatic SOC test integration

Lo et al., 2007

Document ID
18049560312195392000
Author
Lo C
Wang C
Cheng K
Huang J
Wang C
Wang S
Wu C
Publication year
Publication venue
IEEE transactions on very large scale integration (VLSI) systems

External Links

Snippet

The lack of electronic design automation tools for system-on-chip (SOC) test integration increases SOC development time and cost, so SOC test integration tools are important in the success of promoting SOC. We have stressed practical SOC test integration issues …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555Control logic
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