[go: up one dir, main page]

Srinath et al., 2019 - Google Patents

Fault Tolerance in VLSI Circuit with Reducing Rollback Cost using FSM

Srinath et al., 2019

Document ID
18169888337275651904
Author
Srinath G
Samson M
Publication year
Publication venue
2019 3rd International Conference on Computing Methodologies and Communication (ICCMC)

External Links

Snippet

In this generation, the revolutionary growth in nanometer technologies brought the drastic change in reduction of device size, increase in complexity, increasing operating speed and decrease in power consumption, which are more sensitive to various kinds of problems. In a …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation
    • G06F11/1402Saving, restoring, recovering or retrying
    • G06F11/1405Saving, restoring, recovering or retrying at machine instruction level
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled

Similar Documents

Publication Publication Date Title
US8489919B2 (en) Circuits and methods for processors with multiple redundancy techniques for mitigating radiation errors
Ramos et al. Efficient protection of the register file in soft-processors implemented on Xilinx FPGAs
Sabogal et al. Reconfigurable framework for environmentally adaptive resilience in hybrid space systems
Azeem et al. Error recovery technique for coarse-grained reconfigurable architectures
Sogomonyan Self-correction fault-tolerant systems
Lee et al. Survey of error and fault detection mechanisms
US20090249174A1 (en) Fault Tolerant Self-Correcting Non-Glitching Low Power Circuit for Static and Dynamic Data Storage
Ebrahimi et al. ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications
Rollins Hardware and software fault-tolerance of softcore processors implemented in SRAM-based FPGAs
Nicolaidis Circuit-level soft-error mitigation
Reorda et al. A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips
Gong et al. Reliable SEU monitoring and recovery using a programmable configuration controller
Garcia et al. A fault tolerant design methodology for a FPGA-based softcore processor
Hong et al. Design and implementation of fault-tolerant soft processors on FPGAs
US7698511B2 (en) Interface for writing to memories having different write times
Srinath et al. Fault Tolerance in VLSI Circuit with Reducing Rollback Cost using FSM
Cui et al. Mitigating single event upset of FPGA for the onboard bus control of satellite
Schmidt et al. Temporal redundancy latch-based architecture for soft error mitigation
Lee et al. Fault recovery time analysis for coarse-grained reconfigurable architectures
Burlyaev et al. Time-redundancy transformations for adaptive fault-tolerant circuits
Fay et al. An adaptive fault-tolerant memory system for FPGA-based architectures in the space environment
Lanuzza et al. An efficient and low-cost design methodology to improve SRAM-based FPGA robustness in space and avionics applications
Czajkowski et al. SEU mitigation for reconfigurable FPGAs
Cui et al. Mitigating single event upset method for Zynq MPSoC
Vera et al. Fast local scrubbing for field-programmable gate array's configuration memory